MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 272

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.3.3.2 Slave Mode
12-8
MOTOROLA
When the SPI reaches the end of the transmission, it sets the SPIF flag in the SPSR.
If the SPIE bit in the SPCR is set, an interrupt request is generated when SPIF is
asserted. After the SPSR is read with SPIF set, and then the SPDR is read or written
to, the SPIF flag is automatically cleared.
Data transfer is synchronized with the internally-generated serial clock (SCK). Control
bits CPHA and CPOL in SPCR control clock phase and polarity. Combinations of
CPHA and CPOL determine the SCK edge on which the master MCU drives outgoing
data from the MOSI pin and latches incoming data from the MISO pin.
Clearing the MSTR bit in SPCR selects slave mode operation. In slave mode, the SPI
is unable to initiate serial transfers. Transfers are initiated by an external bus master.
Slave mode is typically used on a multimaster SPI bus. Only one device can be bus
master (operate in master mode) at any given time.
When using the SPI in slave mode, include the following steps:
When SPE is set and MSTR is clear, a low state on the SS pin initiates slave mode
operation. The SS pin is used only as an input.
After a byte or word of data is transmitted, the SPI sets the SPIF flag. If the SPIE bit in
SPCR is set, an interrupt request is generated when SPIF is asserted.
Transfer is synchronized with the externally generated SCK. The CPHA and CPOL
bits determine the SCK edge on which the slave MCU latches incoming data from the
MOSI pin and drives outgoing data from the MISO pin.
3. Write to the MDDR to direct the data flow on SPI pins. Configure the SCK (serial
4. Write to the SPCR to assign values for BAUD, CPHA, CPOL, SIZE, LSBF,
5. Enable the slave device.
6. Write appropriate data to the SPI data register to initiate the transfer.
1. Write to the MMCR and interrupt registers. Refer to 12.5 MCCI Initialization for
2. Write to the MPAR to assign the following pins to the SPI: MISO, MOSI, and
3. Write to the MDDR to direct the data flow on SPI pins. Configure the SCK,
4. Write to the SPCR to assign values for CPHA, CPOL, SIZE, LSBF, WOMP, and
clock) and MOSI pins as outputs. Configure MISO and (optionally) SS as in-
puts.
WOMP, and SPIE. Set the MSTR bit to select master operation. Set the SPE
bit to enable the SPI.
more information.
SS. MISO is used for serial data output in slave mode, and MOSI is used for
serial data input. Either or both may be necessary, depending on the particular
application. SCK is the input serial clock. SS selects the SPI when asserted.
MOSI, and SS pins as inputs. Configure MISO as an output.
SPIE. Set the MSTR bit to select master operation. Set the SPE bit to enable
the SPI. (The BAUD field in the SPCR of the slave device has no effect on SPI
operation.)
MULTICHANNEL COMMUNICATION INTERFACE
MC68HC16Y3/916Y3
USER’S MANUAL