MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 214

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.6.3 RC DAC Array
10.6.4 Comparator
10.7 Digital Control Subsystem
10.7.1 Control/Status Registers
10.7.2 Clock and Prescaler Control
10-6
MOTOROLA
The RC DAC array consists of binary-weighted capacitors and a resistor-divider chain.
The array performs two functions: it acts as a sample hold circuit during conversion,
and it provides each successive digital-to-analog comparison voltage to the compara-
tor. Conversion begins with MSB comparison and ends with LSB comparison. Array
switching is controlled by the digital subsystem.
The comparator indicates whether each approximation output from the RC DAC array
during resolution is higher or lower than the sampled input voltage. Comparator output
is fed to the digital control logic, which sets or clears each bit in the successive approx-
imation register in sequence, MSB first.
The digital control subsystem includes control and status registers, clock and prescal-
er control logic, channel and reference select logic, conversion sequence control logic,
and the successive approximation register.
The subsystem controls the multiplexer and the output of the RC array during sample
and conversion periods, stores the results of comparison in the successive-approxi-
mation register, then transfers results to the result registers.
There are two control registers (ADCTL0, ADCTL1) and one status register
(ADSTAT). ADCTL0 controls conversion resolution, sample time, and clock/prescaler
value. ADCTL1 controls analog input selection, conversion mode, and initiation of con-
version. A write to ADCTL0 aborts the current conversion sequence and halts the
ADC. Conversion must be restarted by writing to ADCTL1. A write to ADCTL1 aborts
the current conversion sequence and starts a new sequence with parameters altered
by the write. ADSTAT shows conversion sequence status, conversion channel status,
and conversion completion status.
The following paragraphs are a general discussion of control function. D.6 Analog-to-
Digital Converter Module shows the ADC address map and discusses register bits and
fields.
The ADC clock is derived from the system clock by a programmable prescaler. ADC
clock period is determined by the value of the PRS field in ADCTL0.
The prescaler has two stages. The first stage is a 5-bit modulus counter. It divides the
system clock by any value from 2 to 32 (PRS[4:0] = %00001 to %11111). The second
stage is a divide-by-two circuit. Table 10-3 shows prescaler output values.
ANALOG-TO-DIGITAL CONVERTER
MC68HC16Y3/916Y3
USER’S MANUAL