MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 160

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.7.5.2 Reset States of Pins Assigned to Other MCU Modules
5.7.6 Reset Timing
5-52
MOTOROLA
As a rule, module pins that are assigned to general-purpose I/O ports go into a high-
impedance state following reset. However, during power-on reset, module port pins
may be in an indeterminate state for a short period. Refer to 5.7.7 Power-On Reset for
more information.
The RESET input must be asserted for a specified minimum period for reset to occur.
External RESET assertion can be delayed internally for a period equal to the longest
bus cycle time (or the bus monitor timeout period) in order to protect write cycles from
being aborted by reset. While RESET is asserted, SCIM2 pins are either in an inactive,
high impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic
clocks the signal into an internal latch. The control logic drives the RESET pin low for
an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer
being externally driven to guarantee this length of reset to the entire system.
CS[9:6]/ADDR[22:19]/PC[6:3]
CS[5:3]/FC[2:0]/PC[2:0]
CS10/ADDR23/ECLK
IRQ[7:1]/PF[7:1]
SIZ[1:0]/PE[7:6]
FASTREF/PF0
DSACK0/PE0
DSACK1/PE1
CSE/BGACK
ADDR[18:0]
DATA[15:0]
CSBOOT
CLKOUT
CSM/BG
AS/PE5
CS0/BR
DS/PE4
RESET
Pin(s)
BERR
HALT
R/W
TSC
Table 5-21 SCIM2 Pin Reset States
While RESET
Mode Select
Mode select
Mode select
Pin State
Asserted
Asserted
High-Z
High-Z
High-Z
Output
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
Pin Function
ADDR[18:0]
DATA[15:0]
FASTREF
CSBOOT
CLKOUT
DSACK0
DSACK1
IRQ[7:1]
SIZ[1:0]
CS[9:6]
CS[5:3]
RESET
BERR
HALT
CS10
CS1
CS2
CS0
R/W
TSC
Default Function
DS
AS
Pin State After RESET Released
Pin State
Unknown
Unknown
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
SS
DD
Pin Function
ADDR[22:19]
ADDR[18:0]
DATA[15:0]
CSBOOT
CLKOUT
ADDR23
BGACK
FC[2:0]
RESET
PE[7:6]
PF[7:1]
BERR
HALT
Alternate Function
R/W
TSC
PE5
PE4
PE0
PE1
PF0
BG
BR
MC68HC16Y3/916Y3
USER’S MANUAL
Pin State
Unknown
Unknown
Unknown
Unknown
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
V
V
DD
SS