MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 241

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.3.2.3 Command RAM
11.3.3 QSPI Pins
11.3.4 QSPI Operation
MC68HC16Y3/916Y3
USER’S MANUAL
Command RAM is used by the QSPI in master mode. The CPU16 writes one byte of
control information to this segment for each QSPI command to be executed. The QSPI
cannot modify information in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The periph-
eral chip-select field enables peripherals for transfer. The command control field pro-
vides transfer options.
A maximum of 16 commands can be in the queue. Queue execution by the QSPI pro-
ceeds from the address in NEWQP through the address in ENDQP (both of these
fields are in SPCR2).
The QSPI uses seven pins. These pins can be configured for general-purpose I/O
when not needed for QSPI application.
Table 11-2 shows QSPI input and output pins and their functions.
The QSPI uses a dedicated 80-byte block of static RAM accessible by both the QSPI
and the CPU16 to perform queued operations. The RAM is divided into three seg-
ments. There are 16 command bytes, 16 transmit data words, and 16 receive data
words. QSPI RAM is organized so that one byte of command data, one word of trans-
mit data, and one word of receive data correspond to one queue entry, $0–$F.
The CPU16 initiates QSPI operation by setting up a queue of QSPI commands in com-
mand RAM, writing transmit data into transmit RAM, then enabling the QSPI. The
QSPI executes the queued commands, sets a completion flag (SPIF), and then either
interrupts the CPU16 or waits for intervention.
Peripheral Chip Selects
Master In Slave Out
Master Out Slave In
Slave Select
Serial Clock
Pin Names
Mnemonics
PCS0/SS
PCS[3:1]
MISO
MOSI
SCK
QUEUED SERIAL MODULE
Table 11-2 QSPI Pins
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Serial data input to QSPI
Serial data output from QSPI
Serial data output from QSPI
Serial data input to QSPI
Clock output from QSPI
Clock input to QSPI
Select peripherals
Selects peripherals
Causes mode fault
Initiates serial transfer
Function
MOTOROLA
11-9