MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 136

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.6 Bus Operation
5-28
MOTOROLA
Current
Cycle
NOTES:
10
11
12
13
Internal microcontroller modules are typically accessed in two system clock cycles.
Regular external bus cycles use handshaking between the MCU and external
peripherals to manage transfer size and data. These accesses take three system
clock cycles, with no wait states. During regular cycles, wait states can be inserted as
needed by bus control logic. Refer to 5.6.2 Regular Bus Cycle for more information.
Fast-termination cycles, which are two-cycle external accesses with no wait states,
use chip-select logic to generate handshaking signals internally. Refer to 5.6.3 Fast
Termination Cycles and 5.9 Chip-Selects for more information. Bus control signal tim-
ing, as well as chip-select signal timing, are specified in APPENDIX A ELECTRICAL
CHARACTERISTICS. Refer to the SCIM Reference Manual (SCIMRM/AD) for more
information about each type of bus cycle.
1
2
3
4
5
6
7
8
9
1. Operands in parentheses are ignored by the CPU16 during read cycles.
2. The CPU16 treats misaligned long-word transfers as two misaligned-word transfers.
3. Three byte transfer cases occur only as a result of an aligned long word to 8-bit port transfer.
Byte to 16-bit port (even)
Long word to 16-bit port
Long word to 16-bit port
Three byte to 8-bit port
Byte to 8-bit port (even)
Byte to 16-bit port (odd)
Byte to 8-bit port (odd)
Long word to 8-bit port
Long word to 8-bit port
Word to 16-bit port
Word to 16-bit port
Word to 8-bit port
Word to 8-bit port
Transfer Case
(misaligned)
(misaligned)
(misaligned)
(misaligned
(aligned)
(aligned)
(aligned)
(aligned)
2
2
3
Table 5-12 Operand Alignment
SIZ1
0
0
0
0
1
1
1
1
0
1
0
1
1
SIZ0
1
1
1
1
0
0
0
0
0
0
0
0
1
ADDR0 DSACK1 DSACK0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
DATA
[15:8]
(OP0)
(OP0)
(OP0)
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
MC68HC16Y3/916Y3
USER’S MANUAL
(OP0)
DATA
(OP0)
(OP0)
(OP1)
(OP0)
(OP1)
(OP0)
(OP0)
[7:0]
OP0
OP1
OP0
OP1
OP0
1
Cycle
Next
13
—
—
—
—
—
2
1
3
1
7
3
5