MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 161

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.7.7 Power-On Reset
MC68HC16Y3/916Y3
USER’S MANUAL
If an internal source asserts a reset signal, the reset control logic asserts the RESET
pin for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512
cycles, the control logic continues to assert the RESET pin until the internal reset
signal is negated.
After 512 cycles have elapsed, the RESET pin goes to an inactive, high-impedance
state for ten cycles. At the end of this 10-cycle period, the RESET input is tested.
When the input is at logic level one, reset exception processing begins. If, however,
the RESET input is at logic level zero, reset control logic drives the pin low for another
512 cycles. At the end of this period, the pin again goes to high-impedance state for
ten cycles, then it is tested again. The process repeats until external RESET is
released.
When the SCIM2 clock synthesizer is used to generate system clocks, power-on reset
involves special circumstances related to application of the system and the clock syn-
thesizer power. Regardless of clock source, voltage must be applied to clock synthe-
sizer power input pin V
assumes that V
start-up time. When V
cific crystal parameters and by oscillator circuit design. V
pin state during reset. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for
voltage and timing specifications.
During power-on reset, an internal circuit in the SCIM2 drives the IMB internal
(MSTRST) and external (EXTRST) reset lines. The power-on reset circuit releases the
internal reset line as V
are initialized to the values shown in Table 5-21. When V
erating voltage, the clock synthesizer VCO begins operation. Clock frequency ramps
up to specified limp mode frequency (f
until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SCIM2 clock synthesizer provides clock signals to the other MCU modules. After
the clock is running and MSTRST is asserted for at least four clock cycles, these mod-
ules reset. V
cycles take. Worst case is approximately 15 milliseconds. During this period, module
port pins may be in an indeterminate state. While input-only pins can be put in a known
state by external pull-up resistors, external logic on input/output or output-only pins
during this time must condition the lines. Active drivers require high-impedance buffers
or isolation resistors to prevent conflict.
Figure 5-19 is a timing diagram for power-on reset. It shows the relationships between
RESET, V
V
V
DD
DDSYN
DDSYN
DD
, and bus signals.
ramp time and VCO frequency ramp time determine how long the four
DDSYN
only will cause errant behavior of the MCU.
and all V
DD
DDSYN
is applied before and during reset, which minimizes crystal
DDSYN
ramps up to the minimum operating voltage, and SCIM2 pins
is applied at power-on, start-up time is affected by spe-
DD
for the MCU to operate. The following discussion
pins must be powered. Applying power to
limp
). The external RESET line remains asserted
NOTE
DD
DD
ramp-up time also affects
reaches the minimum op-
MOTOROLA
5-53