MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 305

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

13.11 Pulse-Width Modulation Unit
MC68HC16Y3/916Y3
USER’S MANUAL
An interrupt request can be made when each of the status flags is set. However, op-
eration of the PAI interrupt depends on operating mode. In event counting mode, an
interrupt is requested when the edge being counted is detected. In gated mode, the
request is made when the PAI input changes from active to inactive state. Interrupt re-
quests are enabled by the PAOVI and PAII bits in the TMSK2 register.
Bits in the pulse accumulator control register (PACTL) control the operation of PACNT.
The PAMOD bit selects event counting or gated operation. In event counting mode,
the PEDGE control bit determines whether a rising or falling edge is detected in gated
mode, PEDGE specifies the active state of the gate signal. Bits PACLK[1:0] select the
clock source used in gated mode.
PACTL and PACNT are implemented as one 16-bit register, but can be accessed with
byte or word access cycles. Both registers are cleared at reset, but the PAIS and
PCLKS bits show the state of the PAI and PCLK pins.
The PAI pin can also be used for general-purpose input. The logic state of the PAIS
bit in PACTL shows the state of the pin.
The pulse-width modulation (PWM) unit has two output channels, PWMA and PWMB.
A single clock output from the prescaler multiplexer drives a 16-bit counter that is used
to control both channels. Figure 13-6 is a block diagram of the pulse-width modulation
unit.
GENERAL-PURPOSE TIMER
MOTOROLA
13-17