MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 270

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.3.1 SPI Registers
12.3.1.1 SPI Control Register (SPCR)
12.3.1.2 SPI Status Register (SPSR)
12.3.1.3 SPI Data Register (SPDR)
12-6
MOTOROLA
During an SPI transfer, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line synchronizes shifting and sampling of
the information on the two serial data lines. A slave-select line allows individual
selection of a slave SPI device. Slave devices which are not selected do not interfere
with SPI bus activities. On a master SPI device the slave-select line can optionally be
used to indicate a multiple-master bus contention.
Error-detection logic is included to support interprocessor interfacing. A write-collision
detector indicates when an attempt is made to write data to the serial shift register
while a transfer is in progress. A multiple-master mode-fault detector automatically dis-
ables SPI output drivers if more than one MCU simultaneously attempts to become
bus master.
SPI control registers include the SPI control register (SPCR), the SPI status register
(SPSR), and the SPI data register (SPDR). Refer to D.8.13 SPI Control Register,
D.8.14 SPI Status Register, and D.8.15 SPI Data Register for register bit and field def-
initions.
The SPCR contains parameters for configuring the SPI. The register can be read or
written at any time.
The SPSR contains SPI status information. Only the SPI can set the bits in this
register. The CPU reads the register to obtain status information.
The SPDR is used to transmit and receive data on the serial bus. A write to this register
in the master device initiates transmission or reception of another byte or word. After
a byte or word of data is transmitted, the SPIF status bit is set in both the master and
slave devices.
A read of the SPDR actually reads a buffer. If the first SPIF is not cleared by the time
a second transfer of data from the shift register to the read buffer is initiated, an over-
run condition occurs. In cases of overrun the byte or word causing the overrun is lost.
A write to the SPDR is not buffered and places data directly into the shift register for
transmission.
MULTICHANNEL COMMUNICATION INTERFACE
MC68HC16Y3/916Y3
USER’S MANUAL