MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 336

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

A-10
MOTOROLA
NOTES:
Num
10. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles
11. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time
12. After external RESET negation is detected, a short transition period (approximately 2 t
13. External logic must pull RESET high during this period in order for normal MCU operation to begin.
14. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases.
104
105
1. All AC timing is shown with respect to V
2. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum
3. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low dur-
4. Address access time = (2.5 + WS) t
5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the rel-
6. If multiple chip-selects are used, CS width negated (specification 15) applies to the time from the negation of
7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on
8. Maximum value is equal to (t
9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data set-
of the current operand transfer are complete.
(specification 47A).
SCIM2 drives RESET low for 512 tcyc.
allowable t
external clock input duty cycle and minimum t
ing reset). Does not pertain to an external VCO reference applied while the PLL is enabled (MODCLK pin held
high during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the refer-
ence signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.
Chip select access time = (2 + WS) t
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
ative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to
fall outside the limits shown in specification 9.
a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification
between multiple chip-selects does not apply to chip selects being used for synchronous ECLK cycles.
fast cycle reads. The user is free to use either hold time.
up time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The
data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR
must satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.
AS or DS Valid to Phase 1 Negated
AS or DS Negated to Phase 2 Negated
Minimum t
Xcyc
period is reduced when the duty cycle of the external clock varies. The relationship between
(V
DD
Xcyc
and V
period = minimum t
Table A-6 AC Timing (Continued)
Characteristic
DDSYN
cyc
ELECTRICAL CHARACTERISTICS
/ 2) + 25 ns.
= 5.0 Vdc
cyc
cyc
14
– t
IH
– t
/V
CHAV
14
CLSA
XCHL
IL
Xcyc
levels unless otherwise noted.
– t
– t
10%, V
/ (50% – external clock input duty cycle tolerance).
DICL
is expressed:
DICL
SS
= 0 Vdc, T
Symbol
t
t
SAP1N
SNP2N
A
= T
L
to T
Min
10
10
H
)
1
MC68HC16Y3/916Y3
cyc
USER’S MANUAL
) elapses, then the
Max
—
—
Unit
ns
ns