MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 201

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.1 Overview
9.2 TPUFLASH Control Block
MC68HC16Y3/916Y3
USER’S MANUAL
The TPU flash EEPROM (TPUFLASH) module is a specially designed block-erasable
flash EEPROM (BEFLASH). When placed in TPU mode, it provides a non-volatile, 4-
Kbyte microcode storage space for the time processor unit 2 (TPU2). When the TPU-
FLASH is placed in intermodule bus (IMB) mode, it is no longer used by the TPU2 for
TPU microstore emulation and functions as a normal block-erasable flash EEPROM,
with a block size of 1-Kbtye and a 4-Kbyte array. The TPUFLASH module is used only
in the M68HC916Y3.
The TPUFLASH module consists of a control register block that occupies a fixed po-
sition in MCU address space and a 4-Kbyte flash EEPROM array that can be mapped
to any 4-Kbyte boundary in MCU address space. The array can be configured to reside
in both program and data space, or in program space alone.
The TPUFLASH array can be read as either bytes, words, or long-words. The module
responds to back-to-back IMB accesses, providing two bus cycle (four system clocks)
access for aligned long words. The module can also be programmed to insert up to
three wait states per access, to accommodate migration from slower external devel-
opment memory without re-timing the system.
Both the array and the individual control bits are programmable and erasable under
software control. Program/erase voltage must be supplied via the external V
Data is programmed in byte or word aligned fashion. The module supports both block
and bulk erase modes, and has a minimum program/erase life of 100 cycles. Hard-
ware interlocks protect stored data from corruption if the program/erase voltage to the
TPUFLASH array is enabled accidently. The TPUFLASH array is enabled/disabled by
a combination of DATA12 and the STOP shadow bit after reset. Hardware interlocks
protect stored data from corruption if the program/erase voltage to the TPUFLASH ar-
ray is enabled accidentally. Also, interlocks are provided to ensure TPU mode is not
entered during programming.
The TPUFLASH module control block contains five registers: the TPUFLASH module
configuration register (TFMCR), the TPUFLASH test register (TFTST), the TPU-
FLASH array base address registers (TFBAH and TFBAL), and the TPUFLASH con-
trol register (TFCTL). Four additional words in the control block can contain bootstrap
information when the TPUFLASH is used as bootstrap memory.
Each register in the control block has an associated shadow register that is physically
located in a spare TPUFLASH row. During reset, fields within the registers are loaded
with default information from the shadow registers.
SECTION 9TPU FLASH EEPROM MODULE
TPU FLASH EEPROM MODULE
MOTOROLA
FPE1K
pin.
9-1