MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 435

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

DTL[7:0] — Length of Delay after Transfer
D.7.12 QSPI Control Register 2
SPCR2 — QSPI Control Register 2
SPIFIE — SPI Finished Interrupt Enable
MC68HC16Y3/916Y3
USER’S MANUAL
RESET:
SPIFIE
15
0
where DSCKL[6:0] is in the range of 1 to 127.
When DSCK is zero in a command RAM byte, then DSCKL[6:0] is not used. Instead,
the PCS valid to SCK transition is one-half the SCK period.
When the DT bit is set in a command RAM byte, this field determines the length of the
delay after a serial transfer. The following equation is used to calculate the delay:
where DTL is in the range of 1 to 255.
A zero value for DTL[7:0] causes a delay-after-transfer value of 8192
If DT is zero in a command RAM byte, a standard delay is inserted:
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to
complete conversion. This is controlled by the DT bit in a command RAM byte.
SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt
enable bit. SPCR2 is buffered. New SPCR2 values become effective only after
completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes
execution to restart at the designated location. Reads of SPCR2 return the value of
the register, not the buffer.
0 = QSPI interrupts disabled.
1 = QSPI interrupts enabled.
WREN
14
0
WRTO
13
0
12
0
0
11
0
Delay after Transfer
Standard Delay after Transfer
PCS to SCK Delay
10
ENDQP[3:0]
0
9
0
8
0
7
0
0
=
=
32 DTL[7:0]
----------------------------------- -
DSCKL[6:0]
------------------------------ -
6
0
0
f
f
sys
5
0
0
sys
=
------- -
f
17
sys
4
0
0
3
0
NEWQP[3:0]
2
0
f
sys
$YFFC1C
MOTOROLA
.
1
0
D-57
0
0