MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet
MRF24J40-I/ML
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MRF24J40-I/ML Summary of contents
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... Microchip Technology Inc. MRF24J40 Data Sheet IEEE 802.15.4™ 2.4 GHz RF Transceiver Preliminary DS39776C ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Supports all CCA modes and RSSI/ED • Automatic Packet Retransmit Capability • Hardware Security Engine (AES-128) with CTR, CCM and CBC-MAC modes • Supports Encryption and Decryption for MAC Sublayer and Upper Layer RFP 2 RFN MRF24J40 GND 6 GPIO0 7 GPIO1 8 GPIO5 9 GPIO4 1920 Preliminary LPOSC1 27 LPOSC2 GND ...
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... MRF24J40 1.0 Overview ...................................................................................................................................................................................... 5 2.0 Hardware Description................................................................................................................................................................... 7 3.0 Functional Description................................................................................................................................................................ 89 4.0 Applications .............................................................................................................................................................................. 135 5.0 Electrical Characteristics .......................................................................................................................................................... 141 6.0 Packaging Information.............................................................................................................................................................. 145 Appendix A: Revision History............................................................................................................................................................. 147 Index .................................................................................................................................................................................................. 149 The Microchip Web Site ..................................................................................................................................................................... 153 Customer Change Notification Service .............................................................................................................................................. 153 Customer Support .............................................................................................................................................................................. 153 Reader Response .............................................................................................................................................................................. 154 Product Identification System ...
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... OVERVIEW The MRF24J40 is an IEEE 802.15.4™ Standard com- pliant 2.4 GHz RF transceiver. It integrates the PHY and MAC functionality in a single chip solution. Figure 1-1 shows a simplified block diagram of a MRF24J40 wireless node. The MRF24J40 creates a low-cost, low-power, low data rate (250 or 625 kbps) Wireless Personal Area Network (WPAN) device ...
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... On air packet DS39776C-page highly recommended that the design engineer be familiar with the IEEE 802.15.4-2003 Standard in order with the to best understand the configuration and operation of the MRF24J40. The Standard can be downloaded from the IEEE web site: http://www.ieee.org octets Sequence FCS Number ...
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... PA/LNA RF switches. The power management circuitry consists of an integrated Low Dropout (LDO) voltage regulator. The MRF24J40 can be placed into a very low-current (2 μA typical) Sleep mode. An internal 100 kHz oscillator or 32 kHz external crystal oscillator can be used for Sleep mode timing. ...
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... MRF24J40 2.2 Block Diagram FIGURE 2-1: MRF24J40 ARCHITECTURE BLOCK DIAGRAM DS39776C-page 8 Preliminary © 2010 Microchip Technology Inc. ...
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... External wake-up trigger (must be enabled in software). 16 INT DO Interrupt pin to microcontroller. 17 SDO DO Serial interface data output from MRF24J40. 18 SDI DI Serial interface data input to MRF24J40. 19 SCK DI Serial interface clock Serial interface enable Power Digital circuit power supply. Bypass with a capacitor as close to the pin as possible. ...
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... MRF24J40 2.4 Power and Ground Pins Recommended bypass capacitors are listed in Table 2-2. V pins 1 and 31 require two bypass DD capacitors to ensure sufficient bypass decoupling. Min- imize trace length from the V pin to the bypass DD capacitors and make them as short as possible. TABLE 2-2: RECOMMENDED BYPASS ...
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... MRF24J40 from the host micro- Crystal Oscillator controller used in conjunction with the Sleep modes of the MRF24J40. The WAKE pin is disabled by default. Refer to Section 3.15.2 “Immediate Sleep and Wake-up Mode” for a functional description of the Immediate Sleep and Wake-up modes. ...
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... MRF24J40 via the SDI pin and is clocked in on the rising edge of SCK. Figure 2-5 shows timing for a read operation. Data is sent by the MRF24J40 via the SDO pin and is clocked out on the falling edge of SCK. FIGURE 2-4: SPI PORT WRITE (INPUT) TIMING ...
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... Memory Organization Memory in the MRF24J40 is implemented as static RAM and is accessible via the SPI port. Memory is functionally divided into control registers and data buf- fers (FIFOs), as shown in Figure 2-6. Control registers FIGURE 2-6: MEMORY MAP FOR MRF24J40 Short Address Memory Space ...
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... MRF24J40 2.14.1 SHORT ADDRESS REGISTER INTERFACE The short address memory space contains control registers with a 6-bit address range of 0x00 to 0x3F. Figure 2-7 shows a short address read and Figure 2-8 shows a short address write. The 8-bit SPI transfer FIGURE 2-7: SHORT ADDRESS READ ...
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... SCK SDI SDO © 2010 Microchip Technology Inc. SPI transfer begins with a ‘1’ to indicate a long address transaction followed by the 10-bit register address, Most Significant bit (MSb) first. The read (‘0’) or write (‘1’) transaction Preliminary MRF24J40 th bit indicates DS39776C-page 15 ...
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... EADR6 0x1B 0x0C EADR7 0x1C 0x0D RXFLUSH 0x1D 0x0E Reserved 0x1E Reserved 0x0F 0x1F FIGURE 2-12: LONG ADDRESS CONTROL REGISTER MAP FOR MRF24J40 RFCON0 RSSI 0x200 0x210 0x201 RFCON1 0x211 SLPCON0 0x202 Reserved RFCON2 0x212 0x203 Reserved RFCON3 0x213 ...
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... CONTROL REGISTER SUMMARY TABLE 2-6: SHORT ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 Addr. File Name Bit 7 Bit 6 0x00 RXMCR r r 0x01 PANIDL 0x02 PANIDH 0x03 SADRL 0x04 SADRH 0x05 EADR0 0x06 EADR1 0x07 EADR2 0x08 EADR3 0x09 EADR4 0x0A EADR5 ...
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... MRF24J40 TABLE 2-6: SHORT ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 (CONTINUED) Addr. File Name Bit 7 Bit 6 0x1E ESLOTG23 GTS3-3 GTS3-2 0x1F ESLOTG45 GTS5-3 GTS5-2 0x20 ESLOTG67 r r 0x21 TXPEND MLIFS5 MLIFS4 0x22 WAKECON IMMWAKE REGWAKE 0x23 FRMOFFSET OFFSET7 OFFSET6 0x24 TXSTAT ...
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... TABLE 2-6: SHORT ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 (CONTINUED) Addr. File Name Bit 7 Bit 6 0x30 RXSR r UPSECERR 0x31 INTSTAT SLPIF WAKEIF HSYMTMRIF 0x32 INTCON SLPIE WAKEIE HSYMTMRIE 0x33 GPIO r r 0x34 TRISGPIO r r 0x35 SLPACK SLPACK WAKECNT6 0x36 RFCTL r r 0x37 SECCR2 ...
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... MRF24J40 TABLE 2-7: LONG ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 (CONTINUED) Addr. File Name Bit 7 Bit 6 0x213 Reserved r r 0x214 Reserved r r 0x215 Reserved r r 0x216 Reserved r r 0x217 Reserved r r 0x218 Reserved r r 0x219 Reserved r r 0x21A Reserved r r 0x21B Reserved ...
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... TABLE 2-7: LONG ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 (CONTINUED) Addr. File Name Bit 7 Bit 6 0x246 UPNONCE6 0x247 UPNONCE7 0x248 UPNONCE8 0x249 UPNONCE9 0x24A UPNONCE10 0x24B UPNONCE11 0x24C UPNONCE12 Legend reserved © 2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 UPNONCE<55:48> ...
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... MRF24J40 2.15.3 SHORT ADDRESS CONTROL REGISTERS DETAIL REGISTER 2-1: RXMCR: RECEIVE MAC CONTROL REGISTER (ADDRESS: 0x00) R/W-0 R/W-0 R/W NOACKRSP bit 7 Legend reserved R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Reserved: Maintain as ‘0’ bit 5 NOACKRSP: Automatic Acknowledgement Response bit 1 = Disables automatic Acknowledgement response 0 = Enables automatic Acknowledgement response ...
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... PAN ID Low Byte (PANIDL<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PAN ID High Byte (PANIDH<15:8> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown DS39776C-page 23 ...
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... MRF24J40 REGISTER 2-4: SADRL: SHORT ADDRESS LOW BYTE REGISTER (ADDRESS: 0x03) R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 SADRL<7:0>: Short Address Low Byte bits REGISTER 2-5: SADRH: SHORT ADDRESS HIGH BYTE REGISTER (ADDRESS: 0x04) ...
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... Bit is cleared R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 0 ...
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... MRF24J40 REGISTER 2-9: EADR3: EXTENDED ADDRESS 3 REGISTER (ADDRESS: 0x08) R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<31:24>) bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 EADR<31:24>: 64-Bit Extended Address bits REGISTER 2-10: EADR4: EXTENDED ADDRESS 4 REGISTER (ADDRESS: 0x09) ...
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... Microchip Technology Inc. R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown DS39776C-page 27 ...
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... MRF24J40 REGISTER 2-14: RXFLUSH: RECEIVE FIFO FLUSH REGISTER (ADDRESS: 0x0D) R/W-0 R/W-0 R/W-0 r WAKEPOL WAKEPAD bit 7 Legend reserved R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Reserved: Maintain as ‘0’ bit 6 WAKEPOL: Wake Signal Polarity bit 1 = Wake signal polarity is active-high ...
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... SO ≤ BO ≤ 14). © 2010 Microchip Technology Inc. R/W-1 R/W-1 (1) (1) (1) BO0 SO3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (1) Preliminary MRF24J40 R/W-1 R/W-1 R/W-1 (1) (1) (1) SO2 SO1 SO0 bit Bit is unknown (2) DS39776C-page 29 ...
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... MRF24J40 REGISTER 2-16: TXMCR: CSMA-CA MODE CONTROL REGISTER (ADDRESS: 0x11) R/W-0 R/W-0 R/W-0 NOCSMA BATLIFEXT SLOTTED bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 NOCSMA: No Carrier Sense Multiple Access (CSMA) Algorithm bits 1 = Disable CSMA-CA algorithm when transmitting in Unslotted mode with GTSSWITCH (TXPEND 0x21< ...
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... Refer to IEEE 802.15.4™-2003 Standard, Table 71: MAC PIB Attributes. © 2010 Microchip Technology Inc. R/W-1 R/W-1 R/W-0 (1) (1) (1) MAWD4 MAWD3 MAWD2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary MRF24J40 R/W-0 R/W-1 (1) (1) (1) MAWD1 MAWD0 bit Bit is unknown DS39776C-page 31 ...
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... MRF24J40 REGISTER 2-18: ESLOTG1: GTS1 AND CAP END SLOT REGISTER (ADDRESS: 0x13) R/W-0 R/W-0 R/W-0 GTS1-3 GTS1-2 GTS1-1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 GTS1-<3:0>: End Slot of 1st GTS bits 1111 = 15 • ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-0 R/W-0 (1) (1) (1) TXONT3 TXONT2 TXONT1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary MRF24J40 R/W-0 R/W-0 TICKP1 TICKP0 bit Bit is unknown R/W-0 R/W-1 (1) (1) TXONT0 TICKP8 bit Bit is unknown ...
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... MRF24J40 REGISTER 2-21: PACON0: POWER AMPLIFIER CONTROL 0 REGISTER (ADDRESS: 0x16) R/W-0 R/W-0 R/W-1 (1) (1) PAONT7 PAONT6 PAONT5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 PAONT<7:0>: Power Amplifier Enable On Time Tick bits Power amplifier on time before beginning of packet. PAONT is a 9-bit value. The PAONT8 bit is located in PACON1< ...
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... SYMTICKH<7:1>. Units: tick (50 ns). Default value = 0x028 ( μs). Note 1: Refer to Figure 4-4 for timing diagram. © 2010 Microchip Technology Inc. R/W-0 R/W-1 R/W-0 (1) (1) (1) TXONTS2 TXONTS1 TXONTS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary MRF24J40 R/W-0 R/W-0 (1) (1) (1) TXONT8 TXONT7 bit Bit is unknown DS39776C-page 35 ...
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... MRF24J40 REGISTER 2-24: TXBCON0: TRANSMIT BEACON FIFO CONTROL 0 REGISTER (ADDRESS: 0x1A) R-0 R-0 R bit 7 Legend reserved R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-2 Reserved: Maintain as ‘0’ bit 1 TXBSECEN: TX Beacon FIFO Security Enabled bit 1 = Security enabled ...
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... Bit is cleared at the next triggering of TXN FIFO. © 2010 Microchip Technology Inc. R-0 R/W-0 R/W-0 (1) (4) FPSTAT INDIRECT TXNACKREQ U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (4) (2,4) (3,4) Preliminary MRF24J40 R/W-0 W-0 (2,4) (3,4) TXNSECEN TXNTRIG bit Bit is unknown DS39776C-page 37 ...
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... MRF24J40 REGISTER 2-26: TXG1CON: GTS1 FIFO CONTROL REGISTER (ADDRESS: 0x1 ) R/W-0 R/W-0 R/W-0 TXG1RETRY1 TXG1RETRY0 TXG1SLOT2 TXG1SLOT1 TXG1SLOT0 TXG1ACKREQ TXG1SECEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 TXG1RETRY<1:0>: TX GTS1 FIFO Retry Times bits Write: retry times of packet ...
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... GTS5-0 GTS4-3 GTS4 Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 R/W GTS6 Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 R/W-0 GTS2-1 GTS2-0 bit Bit is unknown R/W-0 R/W-0 R/W-0 GTS4-1 GTS4-0 bit 0 ...
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... MRF24J40 REGISTER 2-31: TXPEND: TX DATA PENDING REGISTER (ADDRESS: 0x21) R/W-1 R/W-0 R/W-0 MLIFS5 MLIFS4 MLIFS3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-2 MLIFS<5:0>: Minimum Long Interframe Spacing bits The minimum number of symbols forming a Long Interframe Spacing (LIFS) period. Refer to IEEE 802.15.4™ ...
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... Refer to Section 3.8.1.4 “Configuring Beacon-Enabled PAN Coordinator” for more information. © 2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 INTL INTL INTL U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary MRF24J40 R/W-0 R/W-0 INTL INTL bit Bit is unknown DS39776C-page 41 ...
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... MRF24J40 REGISTER 2-33: FRMOFFSET: SUPERFRAME COUNTER OFFSET TO ALIGN BEACON REGISTER (ADDRESS: 0x23) R/W-0 R/W-0 R/W-0 (1) (1) OFFSET7 OFFSET6 OFFSET5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 OFFSET<7:0>: Superframe Counter Offset for Align Air Slot Boundary bits For Beacon-Enabled mode device ...
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... TXNSTAT: TX Normal FIFO Release Status bit 1 = Failed, retry count exceeded 0 = Succeeded © 2010 Microchip Technology Inc. R-0 R-0 R-0 TXG2FNT TXG1FNT TXG2STAT U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R-0 R-0 TXG1STAT TXNSTAT bit Bit is unknown DS39776C-page 43 ...
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... MRF24J40 REGISTER 2-35: TXBCON1: TRANSMIT BEACON CONTROL 1 REGISTER (ADDRESS: 0x25) R/W-0 R-0 R/W-1 TXBMSK WU/BCN RSSINUM1 bit 7 Legend reserved R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 TXBMSK: TX Beacon FIFO Interrupt Mask bit Beacon FIFO interrupt is masked Beacon FIFO interrupt is not masked (default) ...
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... GTSON: GTS FIFO Clock Enable bit 1 = Enabled 0 = Disabled (default) bit 2-0 Reserved: Maintain as ‘0’ © 2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 r GTSON Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W bit Bit is unknown DS39776C-page 45 ...
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... MRF24J40 REGISTER 2-37: TXTIME: TX TURNAROUND TIME REGISTER (ADDRESS: 0x27) R/W-0 R/W-1 R/W-0 TURNTIME3 TURNTIME2 TURNTIME1 TURNTIME0 bit 7 Legend reserved R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 TURNTIME<3:0>: Turnaround Time bits Transmission to reception and reception to transmission turnaround time. Refer to IEEE 802.15.4™ ...
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... Microchip Technology Inc. R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown DS39776C-page 47 ...
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... MRF24J40 REGISTER 2-40: SOFTRST: SOFTWARE RESET REGISTER (ADDRESS: 0x2A) R/W-0 R/W-0 R/W bit 7 Legend reserved R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-3 Reserved: Maintain as ‘0’ bit 2 RSTPWR: Power Management Reset bit 1 = Reset power management circuitry (bit is automatically cleared to ‘0’ by hardware) ...
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... AES-CBC-MAC-128 100 = AES-CCM-32 011 = AES-CCM-64 010 = AES-CCM-128 001 = AES-CTR 000 = None (default) © 2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 TXNCIPHER2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 : 0x2C) R/W-0 R/W-0 TXNCIPHER1 TXNCIPHER0 bit Bit is unknown DS39776C-page 49 ...
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... MRF24J40 REGISTER 2-42: SECCON1: SECURITY CONTROL 1 REGISTER (ADDRESS: 0x2D) R/W-0 R/W-0 R/W-0 r TXBCIPHER2 TXBCIPHER1 bit 7 Legend reserved R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Reserved: Read as ‘0’ bit 6-4 TXBCIPHER<2:0>: TX Beacon FIFO Security Suite Select bits ...
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... MSIFS + RFSTBL = aMinSIFSPeriod = 12 symbols. Units: symbol period (16 μs). Default value: 0x5. © 2010 Microchip Technology Inc. R/W-1 R/W-0 R/W-1 RFSTBL0 MSIFS3 MSIFS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-1 MSIFS1 MSIFS0 bit Bit is unknown DS39776C-page 51 ...
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... MRF24J40 REGISTER 2-44: RXSR: RX MAC STATUS REGISTER (ADDRESS: 0x30) R-0 R/W-0 R-0 (1) r UPSECERR BATIND bit 7 Legend reserved R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Reserved: Read as ‘0’ bit 6 UPSECERR: MIC Error in Upper Layer Security Mode bit 1 = MIC error occurred. Write ‘ ...
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... Interrupt bits are cleared to ‘0’ when the INTSTAT register is read. © 2010 Microchip Technology Inc. RC-0 RC-0 RC-0 (1) (1) (1) SECIF RXIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) (1) (1) (1) (1) Preliminary MRF24J40 RC-0 RC-0 RC-0 (1) (1) (1) TXG2IF TXG1IF TXNIF bit Bit is unknown DS39776C-page 53 ...
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... MRF24J40 REGISTER 2-46: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS: 0x32) R/W-1 R/W-1 R/W-1 SLPIE WAKEIE HSYMTMRIE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SLPIE: Sleep Alert Interrupt Enable bit 1 = Disables the Sleep alert interrupt (default Enables the Sleep alert interrupt ...
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... GPIO2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 TRISGP4 TRISGP3 TRISGP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 GPIO1 GPIO0 bit Bit is unknown R/W-0 R/W-0 TRISGP1 TRISGP0 bit Bit is unknown ...
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... Value at POR ‘1’ = Bit is set bit 7 SLPACK: Sleep Acknowledge bit 1 = Places the MRF24J40 to Sleep (automatically cleared to ‘0’ by hardware) bit 6-0 WAKECNT<6:0>: Wake Count bits Main oscillator (20 MHz) start-up timer counter bits. WAKECNT is a 9-bit value. WAKECNT<8:7> bits are located in RFCTL<4:3>. Units: Sleep clock (SLPCLK) period. ...
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... Recommended sequence RFCTL = 0x06 (reset mode) then RFCTL = 0x02 (transmit mode). © 2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (2) WAKECNT8 WAKECNT7 RFRST U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) Preliminary MRF24J40 R/W-0 R/W-0 RFTXMODE RFRXMODE bit Bit is unknown Default value: 0x00. DS39776C-page 57 ...
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... MRF24J40 REGISTER 2-51: SECCR2: SECURITY CONTROL 2 REGISTER (ADDRESS: 0x37) W-0 W-0 R/W-0 UPDEC UPENC TXG2CIPHER2 TXG2CIPHER1 TXG2CIPHER0 TXG1CIPHER2 TXG1CIPHER1 TXG1CIPHER0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 UPDEC: Upper Layer Security Decryption Mode bit 1 = Perform upper layer decryption using TX Normal FIFO. Automatically cleared to ‘ 0 ’ when finished. ...
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... Microchip Technology Inc. 0x38) R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W RXDECINV U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 r TURBO bit Bit is unknown R/W-0 R/W bit Bit is unknown DS39776C-page 59 ...
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... MRF24J40 REGISTER 2-54: BBREG2: BASEBAND 2 REGISTER (ADDRESS: 0x3A) R/W-0 R/W-1 R/W-0 CCAMODE1 CCAMODE0 CCACSTH3 bit 7 Legend reserved R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 CCAMODE<1:0>: Clear Channel Assessment (CCA) Mode bits 11 = CCA Mode 3: Carrier sense with energy above threshold. CCA shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of IEEE 802.15.4™ ...
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... R/W-1 R/W-1 R/W-1 PRECNT2 PRECNT1 PRECNT0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W bit Bit is unknown R/W-0 R-1 r RSSIRDY bit Bit is unknown DS39776C-page 61 ...
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... MRF24J40 REGISTER 2-58: CCAEDTH: ENERGY DETECTION THRESHOLD FOR CCA REGISTER (ADDRESS: 0x3F) R/W-0 R/W-0 R/W-0 CCAEDTH7 CCAEDTH6 CCAEDTH5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 CCAEDTH<7:0>: Clear Channel Assessment (CCA) Energy Detection (ED) Mode bits If the in-band signal strength is greater than the threshold, the channel is busy. The 8-bit value can be mapped to a power level according to RSSI. Refer to Section 3.6 “ ...
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... RFOPT2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 VCOOPT4 VCOOPT3 VCOOPT2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 RFOPT1 RFOPT0 bit Bit is unknown R/W-0 R/W-0 VCOOPT1 VCOOPT0 bit Bit is unknown ...
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... MRF24J40 REGISTER 2-61: RFCON2: RF CONTROL 2 REGISTER (ADDRESS: 0x202) R/W-0 R/W-0 R/W-0 (1) PLLEN r r bit 7 Legend reserved R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 PLLEN: PLL Enable bit 1 = Enabled 0 = Disabled (default) bit 6-0 Reserved: Maintain as ‘0’ Note 1: PLL must be enabled for RF reception or transmission ...
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... R/W-0 R/W-0 R/W-0 (1) (1) BATTH0 Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 R/W-0 (1) 20MRECVR BATEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary MRF24J40 R/W-0 R/W bit Bit is unknown R/W-0 R/W bit Bit is unknown DS39776C-page 65 ...
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... MRF24J40 REGISTER 2-65: RFCON7: RF CONTROL 7 REGISTER (ADDRESS: 0x207) R/W-0 R/W-0 R/W-0 SLPCLKSEL1 SLPCLKSEL0 r bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 SLPCLKSEL<1:0>: Sleep Clock Selection bits 10 = 100 kHz internal oscillator kHz external crystal oscillator bit 5-0 Reserved: Maintain as ‘ ...
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... SLPCAL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 R-0 SLPCAL12 SLPCAL11 SLPCAL10 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R-0 R-0 SLPCAL1 SLPCAL0 bit Bit is unknown R-0 R-0 SLPCAL9 SLPCAL8 bit Bit is unknown ...
Page 68
... MRF24J40 REGISTER 2-69: SLPCAL2: SLEEP CALIBRATION 2 REGISTER (ADDRESS: 0x20B) R-0 R/W-0 R/W-0 SLPCALRDY r r bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SLPCALRDY: Sleep Calibration Ready bit 1 = Sleep calibration count is complete bit 6-5 Reserved: Maintain as ‘0’ ...
Page 69
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 (1) (1) (1) RSSI4 RSSI3 RSSI2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary MRF24J40 U-0 U-0 U-0 — — — bit Bit is unknown R-0 R-0 R-0 (1) (1) (1) RSSI1 ...
Page 70
... MRF24J40 REGISTER 2-72: SLPCON0: SLEEP CLOCK CONTROL 0 REGISTER (ADDRESS: 0x211) R/W-0 R/W-0 R/W bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-2 Reserved: Maintain as ‘0’ bit 1 INTEDGE: Interrupt Edge Polarity bit 1 = Rising edge 0 = Falling edge (default) ...
Page 71
... WAKETIME<7:0>: Wake Time Match Value bits WAKETIME is an 11-bit value that is compared with the Main Counter (MAINCNT) to signal the time to enable (wake-up) the 20 MHz main oscillator when the MRF24J40 is using the Sleep mode timers. Default value: 0x00A. Minimum value: 0x001. Note 1: Rule: WAKETIME > ...
Page 72
... MRF24J40 REGISTER 2-76: REMCNTL: REMAIN COUNTER LOW REGISTER (ADDRESS: 0x224) R/W-0 R/W-0 R/W-0 REMCNT7 REMCNT6 REMCNT5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 REMCNT<7:0>: Remain Counter bits Remain counter is a 16-bit counter. Together with the main counter times events: Beacon Interval (BI) and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices ...
Page 73
... R/W-0 MAINCNT4 MAINCNT3 MAINCNT2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 MAINCNT1 MAINCNT0 bit Bit is unknown R/W-0 R/W-0 MAINCNT9 MAINCNT8 bit Bit is unknown ...
Page 74
... MRF24J40 REGISTER 2-80: MAINCNT2: MAIN COUNTER 2 REGISTER (ADDRESS: 0x228) R/W-0 R/W-0 R/W-0 MAINCNT23 MAINCNT22 MAINCNT21 MAINCNT20 MAINCNT19 MAINCNT18 MAINCNT17 MAINCNT16 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 MAINCNT<23:16>: Main Counter bits Main counter is a 26-bit counter. Together with the remain counter times events: Beacon Interval (BI) and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices ...
Page 75
... Note 1: Refer to Section 4.2 “External PA/LNA Control” for more information. © 2010 Microchip Technology Inc. R/W-0 R/W-1 R/W-0 RSSIWAIT1 RSSIWAIT0 TESTMODE2 TESTMODE1 TESTMODE0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 bit Bit is unknown (1) DS39776C-page 75 ...
Page 76
... MRF24J40 REGISTER 2-83: ASSOEADR0: ASSOCIATED COORDINATOR EXTENDED ADDRESS 0 REGISTER (ADDRESS: 0x230) R/W-0 R/W-0 R/W-0 ASSOEADR7 ASSOEADR6 ASSOEADR5 ASSOEADR4 ASSOEADR3 ASSOEADR2 ASSOEADR1 ASSOEADR0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ASSOEADR<7:0>: 64-Bit Extended Address of Associated Coordinator bits ...
Page 77
... Microchip Technology Inc. R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown DS39776C-page 77 ...
Page 78
... MRF24J40 REGISTER 2-87: ASSOEADR4: ASSOCIATED COORDINATOR EXTENDED ADDRESS 4 REGISTER (ADDRESS: 0x234) R/W-0 R/W-0 R/W-0 ASSOEADR39 ASSOEADR38 ASSOEADR37 ASSOEADR36 ASSOEADR35 ASSOEADR34 ASSOEADR33 ASSOEADR32 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ASSOEADR<39:32>: 64-Bit Extended Address of Associated Coordinator bits ...
Page 79
... Microchip Technology Inc. R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown DS39776C-page 79 ...
Page 80
... MRF24J40 REGISTER 2-91: ASSOSADR0: ASSOCIATED COORDINATOR SHORT ADDRESS 0 REGISTER (ADDRESS: 0x238) R/W-0 R/W-0 R/W-0 ASSOSADR7 ASSOSADR6 ASSOSADR5 ASSOSADR4 ASSOSADR3 ASSOSADR2 ASSOSADR1 ASSOSADR0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ASSOSADR<7:0>: 16-Bit Short Address of Associated Coordinator bits ...
Page 81
... Microchip Technology Inc. R/W-0 R/W-0 R/W-0 UPNONCE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 UPNONCE1 UPNONCE0 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown DS39776C-page 81 ...
Page 82
... MRF24J40 REGISTER 2-95: UPNONCE2: UPPER NONCE SECURITY 2 REGISTER (ADDRESS: 0x242) R/W-0 R/W-0 R/W-0 UPNONCE23 UPNONCE22 UPNONCE21 UPNONCE20 UPNONCE19 UPNONCE18 UPNONCE17 UPNONCE16 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 UPNONCE<23:16>: Upper Nonce bits 13-byte nonce value used in security. ...
Page 83
... Microchip Technology Inc. R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown DS39776C-page 83 ...
Page 84
... MRF24J40 REGISTER 2-99: UPNONCE6: UPPER NONCE SECURITY 6 REGISTER (ADDRESS: 0x246) R/W-0 R/W-0 R/W-0 UPNONCE55 UPNONCE54 UPNONCE53 UPNONCE52 UPNONCE51 UPNONCE50 UPNONCE49 UPNONCE48 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 UPNONCE<55:48>: Upper Nonce bits 13-byte nonce value used in security. ...
Page 85
... Microchip Technology Inc. R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown DS39776C-page 85 ...
Page 86
... MRF24J40 REGISTER 2-103: UPNONCE10: UPPER NONCE SECURITY 10 REGISTER (ADDRESS: 0x24A) R/W-0 R/W-0 R/W-0 UPNONCE87 UPNONCE86 UPNONCE85 UPNONCE84 UPNONCE83 UPNONCE82 UPNONCE81 UPNONCE80 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 UPNONCE<87:80>: Upper Nonce bits 13-byte nonce value used in security. ...
Page 87
... Value at POR ‘1’ = Bit is set bit 7-0 UPNONCE<103:96>: Upper Nonce bits 13-byte nonce value used in security. © 2010 Microchip Technology Inc. R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF24J40 R/W-0 R/W-0 bit Bit is unknown DS39776C-page 87 ...
Page 88
... MRF24J40 NOTES: DS39776C-page 88 Preliminary © 2010 Microchip Technology Inc. ...
Page 89
... Reset before accessing the MRF24J40 to allow the RF circuitry to start up and stabilize. • RESET Pin – The MRF24J40 can be reset by the host microcontroller by asserting the RESET pin 13 low. All control registers will be reset. The MRF24J40 will be released from Reset approxi- mately 250 μ ...
Page 90
... These values differ from the Power-on Reset values and provide improved opera- tional parameters. These settings are normally made once after a Reset. After initialization, MRF24J40 features can be configured for the application. The steps for initialization are shown in Example 3-1. ...
Page 91
... Interrupts The MRF24J40 has one interrupt (INT) pin 16 that signals one of eight interrupt events to the host microcontroller. The interrupt structure is shown in Figure 3-1. Interrupts are enabled via the INTCON (0x32) register. Interrupt flags are located in the INTSTAT (0x31) register. The INTSTAT register ...
Page 92
... MRF24J40 3.4 Channel Selection The MRF24J40 is capable of selecting one of sixteen channel frequencies in the 2.4 GHz band. The desired channel is selected by configuring the CHANNEL bits in the RFCON0 (0x200<7:4>) register. See Table 3-4 for the RFCON0 register setting for channel number and frequency. ...
Page 93
... Clear Channel Assessment (CCA) The CCA signal is an indication to the MAC layer from the PHY layer as to whether the medium is busy or idle. The MRF24J40 provides three methods of performing CCA. Refer to IEEE 802.15.4-2003 Section 6.7.9 “CCA”. 3.5.1 CCA MODE 1: ENERGY ABOVE ...
Page 94
... MRF24J40 3.6 Received Signal Strength Indicator (RSSI)/Energy Detection (ED) RSSI/ED are an estimate of the received signal power within the bandwidth of an IEEE 802.15.4 channel. The RSSI value is an 8-bit value ranging from 0-255. The mapping between the RSSI values with the received power level is shown in Figure 3-3 and is shown in tabular form in Table 3-8 ...
Page 95
... FIGURE 3-3: RSSI vs. RECEIVED POWER (dBm) RSSI -120 -100 © 2010 Microchip Technology Inc. -80 -60 -40 Received Power (dBm) Preliminary MRF24J40 300 250 200 150 100 50 0 -20 0 -50 DS39776C-page 95 ...
Page 96
... MRF24J40 RSSI versus received power (dB) is shown in tabular form in Table 3-8 . TABLE 3-8: RSSI vs. RECEIVED POWER (dB) Received Power RSSI Value RSSI Value (dBm) (hex) -100 0x0 -99 0x0 -98 0x0 -97 0x0 -96 0x0 -95 0x0 -94 0x0 -93 0x0 -92 0x0 -91 0x0 -90 0x0 -89 0x1 -88 0x2 -87 0x5 -86 0x9 -85 0x0D ...
Page 97
... RSSI value will be a very high value if a packet is received with greater signal strength or even if an interferer is present in the channel. Hence, for better approximation of link quality, the MRF24J40 reports the correlation degree between spreading sequences and the incoming chips during the reception of a packet. ...
Page 98
... MRF24J40 3.8.1.1 Superframe Structure The superframe structure is shown in Figure 3-4. A superframe is bounded by the transmission of a beacon frame and can have an active and inactive portion. The coordinator will interact with its PAN only during the active portion of the superframe, and during the inactive portion of the superframe, the coordinator can low-power mode ...
Page 99
... Hold and wait TXGTSxFIFO if Transmit Error Wait for GTS Slot TXGTS1FIFO Transmit Complete TXGTS2FIFO Wait for GTS Slot Preliminary MRF24J40 operation, MRF24J40 uses Transmit Error (clear TXG1TRIG and TXG2TRIG) Transmit Hold and Wait Complete until Next GTS Transmit Error (clear TXG1TRIG ...
Page 100
... BO and SO, the beacon frame will be sent immediately. DS39776C-page 100 3.8.1.5 Configuring Beacon-Enabled GTS Settings for PAN Coordinator The following steps configure the MRF24J40 as a coordinator in a beacon-enabled network with Guaranteed Time Slots: 1. Set the GTSON (GATECLK 0x26 <3>) bit = 1 to enable the GTS FIFO clock. ...
Page 101
... Configure BO (ORDER 0x10<7:4>) value = 0xF. 4. Configure SO (ORDER 0x10<3:0>) value = 0xF. 3.8.2.2 Configuring Nonbeacon-Enabled Device The following steps configure the MRF24J40 as a device in a nonbeacon-enabled network: (ESLOTG1 1. Clear the PANCOORD (RXMCR 0x00<3>) bit = 0 to configure as device. 2. Clear the SLOTTED (TXMCR 0x11<5>) bit = 0 to use Unslotted CSMA-CA mode ...
Page 102
... MRF24J40 TABLE 3-10: REGISTERS ASSOCIATED WITH SETTING UP BEACON-ENABLED AND NONBEACON-ENABLED NETWORKS Addr. Name Bit 7 Bit 6 0x00 RXMCR r r 0x10 ORDER BO3 BO2 0x11 TXMCR NOCSMA BATLIFEXT 0x13 ESLOTG1 GTS1-3 GTS1-2 0x1E ESLOTG23 GTS3-3 GTS3-2 0x1F ESLOTG45 GTS5-3 GTS5-2 0x20 ESLOTG67 r r 0x21 TXPEND ...
Page 103
... Carrier Sense Multiple Access-Collision Avoidance (CSMA-CA) Algorithm MRF24J40 supports both unslotted and slotted CSMA-CA mechanisms, as defined IEEE 802.15.4 Standard. In both CSMA-CA algorithm is implemented using units of time called backoff periods. In slotted CSMA-CA, the back- off period boundaries of every device on the PAN shall be aligned with the superframe slot boundaries of the PAN coordinator ...
Page 104
... To configure the MRF24J40 for Unslotted CSMA-CA mode, clear SLOTTED (TXMCR 0x11<5>) bit = 0. The macMinBE and macMaxCSMABackoff values in the MRF24J40 are set to the IEEE 802.15.4 Standard defaults. To program their values: • macMinBE – Program MACMINBE (TXMCR 0x11<4:3>) bits to a value between 0 and 3 (the IEEE 802.15.4 Standard default is 3). • ...
Page 105
... To configure the MRF24J40 for Slotted CSMA-CA mode, set SLOTTED (TXMCR 0x11<5>) bit = 1. To program the battery life extension bit in the Slotted CSMA-CA mode, set BATLIFEXT (TXMCR 0x11<6>) bit = 1. TABLE 3-11: REGISTERS ASSOCIATED WITH CSMA-CA Addr. Name Bit 7 Bit 6 0x11 TXMCR NOCSMA BATLIFEXT © ...
Page 106
... MRF24J40 3.10 Interframe Spacing (IFS) Interframe Spacing (IFS) allows the MAC sublayer time to process data received by the PHY. The length of the IFS period depends on the size of the frame that transmitted. Frames up to aMaxSIFSFrameSize (18 octets) in length shall be followed by a SIFS period of at least aMinSIFSPeriod (12) symbols. Frames with ...
Page 107
... Start-of-Frame Delimiter (SFD) fields. The preamble sequence enables the receiver to achieve symbol synchronization. The MRF24J40 monitors incoming signals and looks for the preamble of IEEE 802.15.4 packets. When a valid synchronization is obtained, the entire packet is FIGURE 3-9: PACKET RECEPTION ...
Page 108
... MRF24J40 3.11.1 RECEPTION MODES The MRF24J40 can be configured for one of three different Reception modes as shown in Table 3-13. An explanation of each of the modes follows. TABLE 3-13: RECEPTION MODES Receive Mode RXMCR (0x00<1:0>) Normal 00 (default) Error Promiscuous 3.11.1.1 Normal Mode Normal mode accepts only packets with a good CRC and satisfies the requirements of the IEEE 802 ...
Page 109
... RXFIFO without interruption so that received packets are not missed. Note: When the first byte of the RXFIFO is read, the MRF24J40 is ready to receive the next packet. To avoid receiving a packet while the RXFIFO is being read, set the Receive Decode (0x39<2>) to ‘1’ to disable the MRF24J40 from receiving a packet off the air ...
Page 110
... IEEE 802.15.4 Standard defines four frame types: Acknowledgment, Data, Beacon and MAC Command frame. The transmission of the Acknowledgment frame is handled automatically in hardware by the MRF24J40 and is covered in Section 3.13 “Acknowledgement” . Hardware management of the transmission of data, beacon and MAC command frames are handled in four transmit (TX) FIFOs ...
Page 111
... Pending Frame Addressing GTS Sequence Superframe Address Control Number Fields Specification Fields Fields MHR 8 – 127 PSDU PHY Payload PPDU Preliminary MRF24J40 n octets n 2 octets FCS MFR n – octets Command Payload FCS MSDU MFR n – m – k – octets Beacon Payload FCS ...
Page 112
... Security modes. DS39776C-page 112 transmitted using in-line security, the Message Integrity Code (MIC) will be appended in the data payload by the MRF24J40. Refer to Section 3.17 “Security” for more information about transmitting and receiving data in Security mode. MRF24J40 will handle superframe timing, transmission of the beacon and data packets during CAP and CFP ...
Page 113
... Header 0x082 – (0x082 + m – 1) (0x082 + m) – (0x082 + – Transmit the packet by setting the TXBTRIG (TXBCON 0x1A<0>) bit = 1. The bit will be auto- matically cleared by hardware. If the MRF24J40 is configured for Beacon-Enabled mode, the TXBSECEN beacon frame will be transmitted at the beacon Refer to slot time at the beginning of the superframe. In Nonbeacon-Enabled mode, the beacon frame is transmitted at the time of triggering ...
Page 114
... MRF24J40 3.12.4 TX GTSx FIFO In Beacon-Enabled mode, the TX GTSx FIFOs are used for the transmission of data or MAC command frames during the CFP of the superframe. Refer to Section 3.8.1 “Beacon-Enabled Network” for more information about guaranteed time Beacon-Enabled mode. FIGURE 3-14: TX GTS1 AND GTS2 FIFOS FORMAT ...
Page 115
... INDIRECT TXNACKREQ TXG1SLOT2 TXG1SLOT1 TXG1SLOT0 TXG1ACKREQ TXG2SLOT2 TXG2SLOT1 TXG2SLOT0 TXG2ACKREQ CCAFAIL TXG2FNT TXG1FNT HSYMTMRIF SECIF RXIF HSYMTMRIE SECIE RXIE Preliminary MRF24J40 Bit 2 Bit 1 Bit 0 r TXBSECEN TXBTRIG TXNSECEN TXNTRIG TXG1SECEN TXG1TRIG TXG2SECEN TXG2TRIG TXG2STAT TXG1STAT TXNSTAT TXG2IF TXG1IF TXNIF TXG2IE TXG1IE ...
Page 116
... Acknowledgment is not received, retransmit. • TXG2ACKREQ (TXG2CON 0x1D<2>) – When the TX GTS2 FIFO transmits a frame, an Acknowledgment frame is expected Acknowledgment is not received, retransmit. When the frame is transmitted, the MRF24J40 will expect an Acknowledgment macAckWaitDuration Acknowledgment is not received, it will retransmit aMaxFrameRetries. The macAckWaitDuration value can be programmed by the MAWD (ACKTMOUT 0x12< ...
Page 117
... Standard, Section 7.2.1.1.3 “Frame Pending Subfield”. Acknowledgment of a data request MAC command – In response to a data request MAC command, if the MRF24J40 has additional (pending) data, it can set the frame pending bit of the Acknowledgment frame by set- ting DRPACK (ACKTMOUT 0x12<7> This will ...
Page 118
... MRF24J40 3.14 Battery Monitor The MRF24J40 provides a battery monitor feature to monitor the system supplied voltage. A threshold volt- age level (BATTH) can be set and the system supplied voltage can be monitored by the Battery Low Indicator (BATIND) to determine if the voltage is above or below the threshold. The following steps set the threshold and ...
Page 119
... During Sleep, the 20 MHz main oscillator is turned off, disabling the RF, baseband and MAC circuitry. Data is retained in the control and FIFO registers and the MRF24J40 is accessible via the SPI port. There are two Sleep modes: • Timed Sleep Mode • Immediate Sleep and Wake Mode 3 ...
Page 120
... MRF24J40 3.15.1.2 Sleep Clock Calibration The SLPCLK frequency is calibrated by a 20-bit SLPCAL register clocked by the 20 MHz main oscillator (50 ns period). Sixteen samples of the SLPCLK are counted and stored in the SLPCAL register. To perform SLPCLK calibration: 1. Select the source of SLPCLK. 2. Begin calibration by setting the SLPCALEN bit (SLPCAL2 0x20B< ...
Page 121
... OSC1 OSC2 EN 20 MHz Main Oscillator EN Wake Count (WAKECNT<8:0>) SLPCLK Beacon Interval (Beacon-Enabled Coordinator) Inactive Period (Beacon-Enabled Device) ≠ Beacon-Enabled mode (BO ? 15, SLOTTED = 1) SLPACK (SLPACK 0x35<7>) Nonbeacon-Enabled mode (BO = 15, SLOTTED = 0) STARTCNT (MAINCNT3 0x229<7>) Preliminary MRF24J40 MAINCLK WAKECNT = 0 WAKEIF WAKEIFIE DS39776C-page 121 ...
Page 122
... The MRF24J40 alerts the host processor on the bound- ary of the active and inactive portion via a Sleep Alert Interrupt (SLPIF 0x31<7>). The host microcontroller Acknowledges the interrupt (SLPACK 0x35<7>), at which time, the MRF24J40 turns off the 20 MHz main oscillator. As WAKETIME = MAINCNT, the 20 MHz main oscillator is turned on ...
Page 123
... The MRF24J40 alerts the host processor on the bound- ary of the active and inactive portion via a Sleep Alert Interrupt (SLPIF 0x31<7>). The host microcontroller Acknowledges the interrupt (SLPACK 0x35<7>), at which time, the MRF24J40 turns off the 20 MHz main oscillator. As WAKETIME = MAINCNT, the 20 MHz main oscillator is turned on ...
Page 124
... Nonbeacon-Enabled (Coordinator or Device) mode – Figure 3-19 shows the Sleep time line for Non- beacon-Enabled (Coordinator or Device) mode. In this mode, the host processor puts the MRF24J40 to Sleep by setting the STARTCNT (0x229<7>) bit. At the end of the Sleep interval, the MRF24J40 alerts the host processor with a wake-up alert interrupt (0x31< ...
Page 125
... EXAMPLE 3-3: IMMEDIATE SLEEP AND WAKE The steps to prepare the MRF24J40 for immediate sleep and wake up on WAKE pin Prepare WAKE pin: 1. WAKE pin = low 2. RXFLUSH (0x0D) = 0x60 – Enable WAKE pin and set polarity to active-high 3. WAKECON (0x22) = 0x80 – ...
Page 126
... MRF24J40 TABLE 3-21: REGISTERS ASSOCIATED WITH SLEEP Addr. Name Bit 7 Bit 6 0x0D RXFLUSH r WAKEPLOL 0x22 WAKECON IMMWAKE REGWAKE 0x2A SOFTRST r r 0x31 INSTAT SLPIF WAKEIF 0x32 INTCON SLPIE WAKEIE 0x35 SLPACK SLPACK WAKECNT6 0x36 RFCTL r r 0x207 RFCON7 SLPCLKSEL1 SLPCLKSEL0 0x20B SLPCAL2 ...
Page 127
... HSYMTMRH (0x29) reg- ister. A HSYMTMRIF (0x31<5>) interrupt is generated when the count reaches zero. Bit 5 Bit 4 Bit 3 HSYMTMR4 HSYMTMR3 HSYMTMR2 HSYMTMR1 HSYMTMR0 HSYMTMRIF SECIF RXIF HSYMTMRIE SECIE RXIE Preliminary MRF24J40 Bit 2 Bit 1 Bit 0 TXG2IF TXG1IF TXNIF TXG2IE TXG1IE TXNIE DS39776C-page 127 ...
Page 128
... MRF24J40 3.17 Security The MRF24J40 provides a hardware security engine that implements the Advanced Encryption Standard, 128-bit (AES-128) according to the IEEE 802.15.4-2003 Standard. The MRF24J40 supports seven security suites which provide a group of security operations designed to provide security services on MAC and upper layer frames. ...
Page 129
... The TXG1FNT (TXSTAT 0x24<3>) or TXG2FNT (TXSTAT 0x24<4>) bit = 1 indicates if TX GTSx FIFO transmission failed due to not enough time to transmit in the guaranteed time slot. Preliminary MRF24J40 octets n – 5 4/8/16 2 octets Integrity ...
Page 130
... FIFO Address RX FIFO 0x2B0-0x2BF DS39776C-page 130 MRF24J40 issues a Security Interrupt, SECIF (INTSTAT 0x31<4>). The Security Interrupt indicates to the host microcontroller that the received frame was secured. The host micro- controller can choose to decrypt or ignore the frame. The format of the received frame is shown in Example 3-22 ...
Page 131
... Enable Upper Layer Security Encryption mode by setting the UPENC (SECCR2 0x37<6>) bit = 1. © 2010 Microchip Technology Inc. Note: The header length field, as implemented in the MRF24J40 bits long. Therefore, the header length maximum value is 31 octets (bytes). This conforms to the IEEE 802.15.4-2003 Specification. How- ever, ...
Page 132
... The host microcontroller loads the 13-byte NONCE value into the UPNONCE12 through UPNONCE0 (0x240 through 0x24C) registers. Note: The header length field, as implemented in the MRF24J40, is 5-bits long. Therefore, the header length maximum value is 31 octets (bytes). This conforms to the IEEE 802.15.4-2003 Specification. How- ever, ...
Page 133
... Turbo Mode The MRF24J40 provides a Turbo mode to transmit and receive at 625 kbps (2.5 times 250 kbps). This mode enables higher data rates for proprietary protocols. To configure the MRF24J40 for Turbo mode, perform the following steps: 1. Enable Turbo mode by setting the TURBO (BBREG0 0x38< ...
Page 134
... MRF24J40 NOTES: DS39776C-page 134 Preliminary © 2010 Microchip Technology Inc. ...
Page 135
... When using low tolerance components (i.e., ±5%) along with an appropriate ground, the impedance will remain close to the 50 Ω measurement C15 0.5 pF C14 0 C16 0 5.6 nH 0.5 pF Preliminary MRF24J40 C12 0.01 μF RFP RFN DS39776C-page 135 ...
Page 136
... MRF24J40 4.2 External PA/LNA Control External PA, LNA and RF switches can be controlled by the MRF24J40 internal RF state machine. Figure 4-3 shows a typical application circuit with external PA, LNA and RF switches. Setting (0x22F<2:0>) bits to ‘111’ will configure pins, GPIO0, GPIO1 and GPIO2, to operate according to Table 4-1. ...
Page 137
... Bit 5 Bit 4 Bit 3 TXONT4 TXONT3 TXONT2 PAONT5 PAONT4 PAONT3 r PAONTS3 PAONTS2 TXONTS3 TXONTS2 TXONTS1 RFSTBL0 MSIFS3 r RSSIWAIT1 RSSIWAIT0 TESTMODE2 TESTMODE1 TESTMODE0 Preliminary MRF24J40 Beginning of Packet t PAON 18 µs Bit 2 Bit 1 Bit 0 TXONT1 TXONT0 TICKP8 PAONT2 PAONT1 PAONT0 PAONTS1 PAONTS0 PAONT8 TXONTS0 TXONT8 ...
Page 138
... MRF24J40 4.3 PCB Layout Design The following guidelines are intended to aid users in high-frequency PCB layout design. FIGURE 4-5: FOUR BASIC COPPER FR4 LAYERS Note: Care should be taken with all ground lines to prevent breakage. • important to keep the original PCB thickness since any change will affect antenna performance (see total thickness of dielectric) or microstrip lines characteristic impedance ...
Page 139
... MRF24J40 Schematic and Bill of Materials 4.4.1 SCHEMATIC MRF24J40 SCHEMATIC FIGURE 4- 50Ω Antenna C12 C13 0.01 μ C15 L4 0.5 pF 4.7 nH C17 C16 0.3 pF 0.5 pF 5.6 nH Note Not Placed 0.01 μ μ 100 pF L2 C14 RFP 3 RFN GND MRF24J40/ML 7 GPIO0 ...
Page 140
... Chip Capacitor 0402 COG 0.5P C17 Chip Capacitor 0402 COG 0.3P C18 Chip Capacitor 0402 COG 18P C19 Chip Capacitor 0402 COG 18P IC1 MRF24J40-I/ML IC2 Buffer, SC70 Package, NC7SZ125P5X L1 Chip Inductor 0402 10N L2 Chip Inductor 0402 10N L3 Chip Inductor 0402 5.6N L4 Chip Inductor 0402 4 ...
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... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2010 Microchip Technology Inc. (except V )........................ -0. Preliminary MRF24J40 + 0.5V) DD DS39776C-page 141 ...
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... MRF24J40 TABLE 5-1: RECOMMENDED OPERATING CONDITIONS Parameters Ambient Operating Temperature Supply Voltage for RF, Analog and Digital Circuits Supply Voltage for Digital I/O Input High Voltage ( Input Low Voltage ( TABLE 5-2: CURRENT CONSUMPTION Typical Values 25° 3. Chip Mode Condition Sleep Sleep Clock Disabled ...
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... SC SS © 2010 Microchip Technology Inc. Condition Min 2.405 — — — — -33 — 80 bit LSb bit LSb In Characteristic Single Byte Single Byte Preliminary MRF24J40 Typ Max Units — 2.480 GHz 0 — dBm 36 — dB 1.25 — dB -30 — dBc — — ...
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... MRF24J40 NOTES: DS39776C-page 144 Preliminary © 2010 Microchip Technology Inc. ...
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... Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2010 Microchip Technology Inc. Example MRF24J40 -I/ML 0810017 Preliminary MRF24J40 DS39776C-page 145 ...
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... MRF24J40 6.2 Package Details The following sections give the technical details of the packages. 40-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6x0.9 mm Body [QFN] with 0.40 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www ...
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... APPENDIX A: REVISION HISTORY Revision B (October 2008) Rewritten the entire data sheet. Revision C (August 2010) This document includes the updated technical information. © 2010 Microchip Technology Inc. Preliminary MRF24J40 DS39776C-page 147 ...
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... NOTES: © 2010 Microchip Technology Inc. Preliminary MRF24J40 DS39776C-page 148 ...
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... Beacon-Enabled Device Sleep Time Line ............... 119 Example Circuit ........................................................ 129 External PA/LNA ...................................................... 130 IEEE 802.15.4 PHY Packet and MAC Frame Structure ................................................... 4 Interrupt Logic ............................................................ 87 MRF24J40 Architecture ............................................... 6 Nonbeacon-Enabled (Coordinator or Device) Sleep Time Line ............................................... 120 Sleep Clock Generation ........................................... 115 Sleep Mode Counters .............................................. 117 Superframe Structure ................................................. 94 Wireless Node ...
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... MRF24J40 OSC1 (20 MHz Crystal Input) ...................................... 7 OSC2 (20 MHz Crystal Input) ...................................... 7 RESET (Global Hardware Reset Active-Low) .............. 7 RFN (Differential RF Pin, Negative) ............................. 7 RFP (Differential RF Pin, Positive) ............................... 7 SCK (Serial Interface Clock) ........................................ 7 SDI (Serial Interface Data Input) .................................. 7 SDO (Serial Interface Data Output) ............................. 7 V (Charge Pump Power Supply) .............................. 7 ...
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... SPI Port Read (Output) ............................................. 10 SPI Port Write (Input) ................................................ 10 Transmission ................................................................... 106 Associated Registers ............................................... 111 Turbo Mode ..................................................................... 128 Associated Registers ............................................... 128 TX Beacon FIFO .............................................................. 109 TX FIFOs Frame Structure .............................................. 108 TX GTSx FIFO ................................................................. 110 TX Normal FIFO .............................................................. 108 W WWW Address ................................................................ 146 WWW, On-Line Support ...................................................... 2 Preliminary MRF24J40 DS39776C-page 151 ...
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... MRF24J40 NOTES: DS39776C-page 152 Preliminary © 2010 Microchip Technology Inc. ...
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... Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com Preliminary MRF24J40 should contact their distributor, DS39776C-page 153 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: MRF24J40 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... Temperature Range I = -40°C to +85°C (Industrial) Package ML = QFN (Plastic Quad Flat, No Lead Tape and Reel © 2010 Microchip Technology Inc. XXX Example: a) MRF24J40-I/ML: Industrial temperature, Pattern QFN package. b) MRF24J40T-I/ML: Industrial temperature, QFN package, tape and reel. Preliminary MRF24J40 . DS39776C-page 155 ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2010 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...