MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 120

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.15.1.2
The SLPCLK frequency is calibrated by a 20-bit
SLPCAL register clocked by the 20 MHz main oscillator
(50 ns period). Sixteen samples of the SLPCLK are
counted and stored in the SLPCAL register. To perform
SLPCLK calibration:
1.
2.
3.
The 20-bit SLPCAL value is contained in registers,
SLPCAL2, SLPCAL1 and SLPCAL0 (0x20B<3:0>,
0x20A and 0x209). The Sleep clock period is calculated
as shown in Equation 3-1.
EQUATION 3-1:
The SLPCLK frequency can be slowed by setting the
Sleep Clock Division (SLPCLKDIV) bits (SLPCON1
0x220<4:0>).
3.15.1.3
Figure 3-16 shows the Sleep mode counters. A
summary of the counters are:
Main Counter (0x229<1:0>, 0x228, 0x227, 0x226) – A
26-bit counter clocked by SLPCLK. Together with the
Remain Counter times events as listed in Table 3-19.
Remain Counter (0x225, 0x224) – A 16-bit counter
clocked by MAINCLK. Together with the Main Counter
times events as listed in Table 3-19.
DS39776C-page 120
MRF24J40
Select the source of SLPCLK.
Begin calibration by setting the SLPCALEN bit
(SLPCAL2 0x20B<4>) to ‘1’. Sixteen samples of
the SLPCLK are counted and stored in the
SLPCAL register.
Calibration is complete when the SLPCALRDY
bit (SLPCAL2 0x20B<7>) is set to ‘1’.
P
SLPCAL
Sleep Clock Calibration
Sleep Mode Counters
= SLPCAL * 50 ns/16
Preliminary
Wake Time (0x223<2:0>, 0x222) – An 11-bit value that
is compared with the main counter value to signal the
time to enable (wake-up) the 20 MHz main oscillator.
Table 3-20 gives the recommended values for
WAKETIME depending on the SLPCLK frequency.
Wake Count (0x36<4:3>, 0x35<6:0>) – A 9-bit counter
clocked by SLPCLK. During the time the wake counter
is counting, the 20 MHz main oscillator is starting up,
stabilizing and disabled to the RF, baseband and MAC
circuitry. The recommended wake count period is 2 ms
to allow the 20 MHz main oscillator to stabilize.
Table 3-20 gives the recommended values for
WAKECNT depending on the SLPCLK frequency.
TABLE 3-19:
TABLE 3-20:
Beacon-Enabled
Coordinator
Beacon-Enabled Device
Nonbeacon-Enabled
Coordinator or Device
SLPCLK
100 kHz
Source
32 kHz
Mode
SLPCLKDIV
0x01
0x00
MAIN AND REMAIN COUNTER
TIMED EVENTS
WAKE TIME AND WAKE
COUNT RECOMMENDED
VALUES
© 2010 Microchip Technology Inc.
WAKETIME
(2.1 ms)
0x0D2
Beacon Interval (BI)
0x045
Inactive Period
Sleep Interval
Timed Event
WAKECNT
(2 ms)
0x0C8
0x042