MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 28

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 2-14:
DS39776C-page 28
MRF24J40
bit 7
Legend:
R = Readable bit
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
-n = Value at POR
bit 7
R/W-0
r
Reserved: Maintain as ‘0’
WAKEPOL: Wake Signal Polarity bit
1 = Wake signal polarity is active-high
0 = Wake signal polarity is active-low (default)
WAKEPAD: Wake I/O Pin Enable bit
1 = Enable wake I/O pin
0 = Disable wake I/O pin (default)
Reserved: Maintain as ‘0’
CMDONLY: Command Frame Receive bit
1 = Only command frames are received, all other frames are filtered out
0 = All valid frames are received (default)
DATAONLY: Data Frame Receive bit
1 = Only data frames are received, all other frames are filtered out
0 = All valid frames are received (default)
BCNONLY: Beacon Frame Receive bit
1 = Only beacon frames are received, all other frames are filtered out
0 = All valid frames are received (default)
RXFLUSH: Reset Receive FIFO Address Pointer bit
1 = Resets the RXFIFO Address Pointer to zero. RXFIFO data is not modified. Bit is automatically
WAKEPOL
R/W-0
cleared to ‘0’ by hardware.
RXFLUSH: RECEIVE FIFO FLUSH REGISTER (ADDRESS: 0x0D)
r = reserved
W = Writable bit
‘1’ = Bit is set
WAKEPAD
R/W-0
R/W-0
Preliminary
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CMDONLY
R/W-0
DATAONLY
R/W-0
© 2010 Microchip Technology Inc.
x = Bit is unknown
BCNONLY
R/W-0
RXFLUSH
W-0
bit 0