MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 70

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 2-72:
REGISTER 2-73:
DS39776C-page 70
MRF24J40
bit 7
Legend:
R = Readable bit
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
bit 5
bit 4-0
Note 1:
-n = Value at POR
bit 7-2
-n = Value at POR
bit 7-6
R/W-0
R/W-0
r
r
Ensure that the interrupt polarity matches the interrupt pin polarity on the host microcontroller.
If the Sleep Clock Selection, SLPCLKSEL (0x207<7:6), is the internal oscillator (100 kHz), set
SLPCLKDIV to a minimum value of 0x01.
Reserved: Maintain as ‘0’
CLKOUTEN: CLKOUT Pin Enable bit
The CLKOUT pin 26 feature has been discontinued. It is recommended that it be disabled.
1 = Disable (recommended)
0 = Enable (default)
SLPCLKDIV<4:0>: Sleep Clock Divisor bits
Sleep clock is divided by 2
Reserved: Maintain as ‘0’
INTEDGE: Interrupt Edge Polarity bit
1 = Rising edge
0 = Falling edge (default)
SLPCLKEN: Sleep Clock Enable bit
1 = Disabled
0 = Enabled (default)
R/W-0
R/W-0
r
SLPCON0: SLEEP CLOCK CONTROL 0 REGISTER (ADDRESS: 0x211)
SLPCON1: SLEEP CLOCK CONTROL 1 REGISTER (ADDRESS: 0x220)
r
r = reserved
W = Writable bit
‘1’ = Bit is set
CLKOUTEN SLPCLKDIV4 SLPCLKDIV3 SLPCLKDIV2 SLPCLKDIV1 SLPCLKDIV0
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
r
n
, where n = SLPCLKDIV.
R/W-0
R/W-0
Preliminary
r
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
r
(1)
Default value: 0x00.
R/W-0
R/W-0
r
© 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
INTEDGE
R/W-0
R/W-0
(1)
SLPCLKEN
R/W-0
R/W-0
bit 0
bit 0