MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 119

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.15
The MRF24J40 can be placed into a low-current Sleep
mode. During Sleep, the 20 MHz main oscillator is turned
off, disabling the RF, baseband and MAC circuitry. Data
is retained in the control and FIFO registers and the
MRF24J40 is accessible via the SPI port. There are two
Sleep modes:
• Timed Sleep Mode
• Immediate Sleep and Wake Mode
3.15.1
The Timed Sleep Mode uses several counters to time
events for the Sleep and wake-up of the MRF24J40.
The following sections cover Sleep clock generation,
calibration and counters.
FIGURE 3-15:
The 100 kHz internal oscillator requires no external
components. However, it is not as accurate or stable as
the 32 kHz external crystal oscillator. It is recom-
mended that it be calibrated before use. See
Section 3.15.1.2 “Sleep Clock Calibration” below for
the Sleep clock calibration procedure.
To select the 100 kHz internal oscillator as the source
of SLPCLK, set the SLPCLKSEL bits (RFCON7
0x207<7:6> to ‘10’)
© 2010 Microchip Technology Inc.
LPOSC2
LPOSC1
Sleep
TIMED SLEEP MODE
(SLPCON0 0x211<0>)
SLPCLKEN
SLEEP CLOCK GENERATION
EN
EN
External Oscillator
Internal Oscillator
100 kHz
32 kHz
(RFCON7 0x207<7:6>)
SLPCLKSEL
01
10
Preliminary
(SLPCLKDIV<4:0>)
Sleep Clock Divisor
3.15.1.1
Figure 3-15 shows the Sleep clock generation circuitry.
The Sleep Clock (SLPCLK) frequency is selectable
between a 100 kHz internal oscillator or a 32 kHz
external crystal oscillator. The Sleep Clock Enable
(SLPCLKEN) bit in the SLPCON0 (0x211<0>) register
can enable (SLPCLKEN = 0; default setting) or disable
(SLPCLKEN = 1) the Sleep clock oscillators. The
SLPCLK frequency can be further divided by the Sleep
Clock Divisor (SLPCLKDIV) 0x220<4:0> bits. The
SLPCLK frequency can be calibrated; the procedure is
listed in Section 3.15.1.2 “Sleep Clock Calibration”
below.
The 32 kHz external crystal oscillator provides better
frequency accuracy and stability than the 100 kHz
internal oscillator. The 32 kHz external crystal oscillator
external circuitry is explained in detail in Section 2.7
“32 kHz External Crystal Oscillator” .
To select the 32 kHz external crystal oscillator as the
source of SLPCLK, set the SLPCLKSEL bits (RFCON7
0x207<7:6>) to ‘01’.
Count 16 SLPCLK Periods
MAINCLK
Sleep Clock Generation
(SLPCAL2 0x20B<4>)
SLPCALEN
Sleep Calibration Counter
(SLPCAL<19:0>)
MRF24J40
SLPCLK
(SLPCAL2 0x20B<7>)
DS39776C-page 119
SLPCALRDY