MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 132

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.17.4
To decrypt an upper layer frame, perform the following
steps:
1.
2.
TABLE 3-26:
DS39776C-page 132
MRF24J40
0x24C UPNONCE12
0x240 UPNONCE0
0x241 UPNONCE1
0x242 UPNONCE2
0x243 UPNONCE3
0x244 UPNONCE4
0x245 UPNONCE5
0x246 UPNONCE6
0x247 UPNONCE7
0x248 UPNONCE8
0x249 UPNONCE9
0x24A UPNONCE10
0x24B UPNONCE11
Addr.
0x1C TXG1CON
0x1D TXG2CON
0x2C SECCON0
0x1A TXBCON0
0x1B TXNCON
0x24 TXSTAT
0x2D SECCON1
0x30 RXSR
0x31 INTSTAT
0x32 INTCON
0x37 SECCR2
Note:
The host microcontroller loads the TXNFIFO
with the upper layer frame for decryption into the
TXNFIFO
Figure 3-23. The header length field indicates
the number of octets (bytes) that are not
encrypted.
The host microcontroller loads the 13-byte
NONCE value into the UPNONCE12 through
UPNONCE0 (0x240 through 0x24C) registers.
Name
UPPER LAYER DECRYPTION
The header length field, as implemented in
the MRF24J40, is 5-bits long. Therefore,
the header length maximum value is
31 octets (bytes). This conforms to the
IEEE 802.15.4-2003 Specification. How-
ever,
IEEE 802.15.4-2006 Standard. The work
around is to:
- Use a header length no longer than
- Implement a security algorithm in the
31 octets (bytes)
upper layers
using
REGISTERS ASSOCIATED WITH SECURITY
TXG1RETRY1 TXG1RETRY0
TXG2RETRY1 TXG2RETRY0
TXNRETRY1
SECIGNORE
it
UPDEC
SLPIF
SLPIE
Bit 7
does
r
r
r
r
the
not
TXBCIPHER2 TXBCIPHER1
TXNRETRY0
UPSECERR
SECSTART
format
WAKEIF
WAKEIE
UPENC
Bit 6
r
r
conform
shown
TXG2CIPHER2 TXG2CIPHER1 TXG2CIPHER0 TXG1CIPHER2 TXG1CIPHER1 TXG1CIPHER0
HSYMTMRIE
HSYMTMRIF
TXG1SLOT2
TXG2SLOT2
RXCIPHER2
CCAFAIL
BATIND
to
Bit 5
r
r
in
the
Preliminary
TXBCIPHER0
TXG1SLOT1
TXG2SLOT1
RXCIPHER1
TXG2FNT
FPSTAT
SECIF
SECIE
Bit 4
UPNONCE<103:96>
r
r
UPNONCE<23:16>
UPNONCE<31:24>
UPNONCE<39:32>
UPNONCE<47:40>
UPNONCE<55:48>
UPNONCE<63:56>
UPNONCE<71:64>
UPNONCE<79:72>
UPNONCE<87:80>
UPNONCE<95:88>
UPNONCE<15:8>
UPNONCE<7:0>
3.
4.
5.
6.
7.
8.
9.
Program the 128-bit security key into the TX
Normal FIFO Security Key FIFO memory
address, 0x280 through 0x28F.
Select the security suite and program the
TXNCIPHER (SECCON0 0x2C<2:0>) bits. The
security suite selection values are shown in
Table 3-24.
Enable Upper Layer Security Decryption mode by
setting the UPDEC (SECCR2 0x37<7>) bit = 1.
Start Decrypting the frame by setting the
TXNTRIG (TXNCON 0x1B<0>) bit to 1.
A TXNIF (INTSTAT 0x31<0>) interrupt will be
issued. The TXNSTAT (TXSTAT 0x24<0>) bit = 0
indicates that the decryption process has
completed.
Check if a MIC error occurred by reading the
UPSECERR (0x30<6>) bit:
UPSECERR = 0: No MIC error
UPSECERR = 1: MIC error occurred; write ‘1’
The decrypted frame is available in the TXNFIFO
and can be read by the host microcontroller.
TXG1SLOT0
TXG2SLOT0
RXCIPHER0
INDIRECT
TXG1FNT
RXIE
Bit 3
RXIF
r
r
r
TXG1ACKREQ
TXG2ACKREQ
TXNCIPHER2
TXNACKREQ
SECDECERR
TXG2STAT
TXG2IF
TXG2IE
Bit 2
r
r
© 2010 Microchip Technology Inc.
to clear error
TXNCIPHER1
TXG1SECEN
TXG2SECEN
TXBSECEN
TXNSECEN
TXG1STAT
DISDEC
TXG1IF
TXG1IE
Bit 1
r
TXNCIPHER0
TXG1TRIG
TXG2TRIG
TXBTRIG
TXNTRIG
TXNSTAT
DISENC
TXNIF
TXNIE
Bit 0
r