MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 94

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.6
RSSI/ED are an estimate of the received signal power
within the bandwidth of an IEEE 802.15.4 channel. The
RSSI value is an 8-bit value ranging from 0-255. The
mapping between the RSSI values with the received
power level is shown in Figure 3-3 and is shown in
tabular form in Table 3-8. The number of symbols to
average can be changed by programming the
RSSINUM (TXBCON1 0x25<5:4>) bits.
The programmer can obtain the RSSI/ED value in one
of two methods.
FIGURE 3-2:
TABLE 3-7:
DS39776C-page 94
MRF24J40
0x210 RSSI
Addr.
0x3E BBREG6
0x25 TXBCON1
Frame Length
1 Octet
Received Signal Strength
Indicator (RSSI)/Energy Detection
(ED)
Name
REGISTERS ASSOCIATED WITH RSSI/ED
RSSIMODE1 RSSIMODE2
TXBMSK
RSSI7
PACKET FORMAT IN RX FIFO
Bit 7
N Octets
Header
WU/BCN
RSSI6
Bit 6
M Octets
Payload
RSSINUM1 RSSINUM0
RSSI5
Bit 5
Preliminary
r
RSSI4
Bit 4
r
3.6.1
In this mode, the host microcontroller sends a request
to calculate RSSI, then waits until it is done and then
reads the RSSI value. The steps are:
1.
2.
3.
3.6.2
The RSSI value is appended at the end of each
successfully received packet.
To enable RSSI Mode 2, set RSSIMODE2 = 1
(0x3E<6>). The RSSI value will be appended to the
RXFIFO as shown in Figure 3-2.
2 Octets
FCS
Set RSSIMODE1 0x3E<7> – Initiate RSSI
calculation.
Wait until RSSIRDY 0x3E<0> is set to ‘1’ – RSSI
calculation is complete.
Read RSSI 0x210<7:0> – The RSSI register
contains the averaged RSSI received power
level for 8 symbol periods.
RSSI3
Bit 3
RSSI FIRMWARE REQUEST (RSSI
MODE1)
APPENDED RSSI TO THE
RECEIVED PACKET (RSSI MODE 2)
r
r
1 Octet
RSSI2
Bit 2
LQI
© 2010 Microchip Technology Inc.
r
r
RSSI1
Bit 1
r
r
1 Octet
RSSI
RSSIRDY
RSSI0
Bit 0
r