MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 38

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 2-26:
REGISTER 2-27:
DS39776C-page 38
MRF24J40
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-3
bit 2
bit 1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-3
bit 2
bit 1
bit 0
TXG1RETRY1 TXG1RETRY0 TXG1SLOT2 TXG1SLOT1 TXG1SLOT0 TXG1ACKREQ TXG1SECEN
TXG2RETRY1 TXG2RETRY0 TXG2SLOT2 TXG2SLOT1 TXG2SLOT0 TXG2ACKREQ TXG2SECEN TXG2TRIG
R/W-0
R/W-0
TXG2RETRY<1:0>: TX GTS2 FIFO Retry Times bits
Write: retry times of packet
Read: number of retry times of the successfully transmitted packet
TXG2SLOT<2:0>: GTS Slot that TX GTS2 FIFO Occupies bits
TXG2ACKREQ: TX GTS2 FIFO Acknowledgement Request bit
Transmit a frame with Acknowledgement frame expected. If Acknowledgement is not received, retransmit.
1 = Acknowledgement requested
0 = No Acknowledgement requested (default)
TXG2SECEN: TX GTS2 FIFO Security Enabled bit
1 = Security enabled
0 = Security disabled (default)
TXG2TRIG: Transmit Frame in TX GTS2 FIFO bit
1 = Transmit the frame in the TX GTS2 FIFO; bit is automatically cleared by hardware
TXG1RETRY<1:0>: TX GTS1 FIFO Retry Times bits
Write: retry times of packet
Read: number of retry times of the successfully transmitted packet
TXG1SLOT<2:0>: GTS Slot that TX GTS1 FIFO Occupies bits
TXG1ACKREQ: TX GTS1 FIFO Acknowledgement Request bit
Transmit a frame with Acknowledgement frame expected. If Acknowledgement is not received, retransmit.
1 = Acknowledgement requested
0 = No Acknowledgement requested (default)
TXG1SECEN: TX GTS1 FIFO Security Enabled bit
1 = Security enabled
0 = Security disabled (default)
TXG1TRIG: Transmit Frame in TX GTS1 FIFO bit
1 = Transmit the frame in the TX GTS1 FIFO; bit is automatically cleared by hardware
R/W-0
R/W-0
TXG1CON: GTS1 FIFO CONTROL REGISTER (ADDRESS: 0x1 )
TXG2CON: GTS2 FIFO CONTROL REGISTER (ADDRESS: 0x1 )
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
R/W-0
© 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
C
D
R/W-0
TXG1TRIG
W-0
W-0
bit 0
bit 0