MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 109

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The RXFIFO is a 128-byte dual port buffer. The
RXMAC circuitry places the packet into the RXFIFO
sequentially, byte by byte, using an internal pointer.
The internal pointer is reset one of three ways:
1.
2.
3.
EXAMPLE 3-2:
3.11.5
If the received packet has the security enabled bit set to
‘1’ (bit 3 of the frame control field; refer to IEEE 802.15.4
Standard, Section 7.2.1.1 “Frame Control Field”) a
TABLE 3-15:
© 2010 Microchip Technology Inc.
Addr.
0x00 RXMCR
0x0D RXFLUSH
0x2A SOFTRST
0x31 INSTAT
0x32 INTCON
0x39 BBREG1
Example steps to read the RXFIFO:
1.
2.
3.
4.
5.
6.
7.
When the host microcontroller reads the first
byte of the packet.
Manually by setting the RXFLUSH (0x0D<0>)
bit. The bit is automatically cleared to ‘0’ by
hardware.
Software Reset (see Section 3.1 “Reset” for
more information).
Receive RXIF interrupt.
Disable host microcontroller interrupts.
Set RXDECINV = 1; disable receiving packets off air.
Read address, 0x300; get RXFIFO frame length value.
Read RXFIFO addresses, 0x301 through (0x300 + Frame Length + 2); read packet data plus LQI and RSSI.
Clear RXDECINV = 0; enable receiving packets.
Enable host microcontroller interrupts.
Name
SECURITY
REGISTERS ASSOCIATED WITH RECEPTION
SLPIF
SLPIE
Bit 7
STEPS TO READ RXFIFO
r
r
r
r
WAKEPOL
WAKEIF
WAKEIE
Bit 6
r
r
r
HSYMTMRIF
HSYMTMRIE
NOACKRSP
WAKEPAD
Bit 5
r
r
Preliminary
SECIF
SECIE
Bit 4
r
r
r
r
The RXFIFO can only hold one packet at a time. It is
highly recommended that the host microcontroller read
the entire RXFIFO without interruption so that received
packets are not missed.
Example 3-2 shows example steps to read the
RXFIFO.
Security Interrupt (SECIF 0x31<4>) is issued. The host
microcontroller can then decide to decrypt or ignore the
packet. See Section 3.17 “Security” for more
information.
Note:
PANCOORD
CMDONLY
RXIF
RXIE
Bit 3
r
r
When the first byte of the RXFIFO is read,
the MRF24J40 is ready to receive the next
packet. To avoid receiving a packet while
the RXFIFO is being read, set the Receive
Decode
(0x39<2>) to ‘1’ to disable the MRF24J40
from receiving a packet off the air. Once
the data is read from the RXFIFO, the
RXDECINV should be cleared to ‘0’ to
enable packet reception.
DATAONLY
RXDECINV
RSTPWR
COORD
TXG2IE
TXG2IF
Bit 2
Inversion
MRF24J40
BCNONLY
ERRPKT
TXG1IE
RSTBB
TXG1IF
Bit 1
(RXDECINV)
DS39776C-page 109
r
RXFLUSH
RSTMAC
PROMI
TXNIF
TXNIE
Bit 0
r
bit