IPR-FFT Altera, IPR-FFT Datasheet - Page 11

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–8. Resource Usage with the Burst Data Flow Architecture—Cyclone III Devices
Table 1–9. Performance with the Burst Data Flow Architecture—Cyclone III Devices (Part 1 of 2)
© December 2010 Altera Corporation
Note to
(1) When using the burst data flow architecture, you can specify the number of engines in the FFT MegaWizard interface. You may choose from
Points
1024
4096
1024
4096
1024
4096
1024
4096
1024
Points
256
256
256
256
256
4096
1024
4096
1024
4096
1024
4096
1024
4096
256
256
256
256
one to two single-output engines in parallel, or from one, two, or four quad-output engines in parallel.
Table
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Single Output
Single Output
Single Output
Single Output
Single Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Single Output
Single Output
Single Output
Single Output
Single Output
Single Output
1–8:
Architecture
Architecture
Engine
Engine
Table 1–9
/2 adders complex multiplier structure, for data and twiddle width 16, for Cyclone III
(EP3C10F256C6) devices.
Engines
Number of
Engines
Number of
lists performance with burst data flow architecture, using the 4 multipliers
1
1
1
2
2
2
4
4
4
1
1
1
2
2
1
2
2
2
4
4
4
1
1
1
2
2
2
(1)
(2)
(MHz)
fMAX
232
246
215
244
216
219
225
202
204
250
223
227
235
221
Combinational
3277
5141
5248
5304
9012
9144
9241
1449
1518
1598
2131
2185
2237
LUTs
Calculation Time
Cycles
24705
1069
5167
2607
1378
1115
5230
2652
235
162
557
118
340
585
Transform
Time (μs)
Registers
24.07
23.43
108.7
10659
10868
11058
Logic
1.01
4.35
0.66
2.58
11.9
0.52
1.68
6.76
4.45
2.49
4044
5872
6064
6240
1499
1545
1591
2460
2536
2612
12
(2)
Data Load & Transform
Cycles
28801
Memory
2093
9263
1581
6703
1364
5474
1371
6344
3676
229632
229632
229632
147712
229632
491
397
374
841
14592
57600
14592
57600
37120
14592
57600
(Bits)
9472
Calculation
(Part 2 of 2)
Time (μs)
Memory
126.73
43.15
30.59
26.87
28.42
16.64
(M9K)
2.12
8.51
1.63
7.31
1.66
6.75
5.48
3.58
FFT MegaCore Function User Guide
28
15
15
28
28
28
28
19
11
28
3
6
9
Cycles
Block Throughput
32898
Blocks
1291
6157
1163
5133
1099
4633
1628
7279
1098
4701
331
299
283
9 × 9
24
48
48
48
96
96
96
16
16
16
8
8
8
(3)
Time (μs)
144.75
28.68
23.43
22.74
21.28
1.43
5.25
1.23
5.38
1.26
5.43
32.6
4.67
(MHz)
6.5
215
244
216
219
225
202
204
250
223
227
235
221
219
f
MAX
1–7