IPR-FFT Altera, IPR-FFT Datasheet - Page 39

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
FFT Processor Engine Architectures
Mixed Radix-4/2 Architecture
Quad-Output FFT Engine Architecture
Figure 3–1. Quad-Output FFT Engine
© December 2010 Altera Corporation
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3. The next 8 clock cycles feed the higher order calculations stored in the delay
Subsequent data stages use the same principles. However, the delays in the feedback
path are adjusted accordingly.
Mixed radix-4/2 architecture combines the advantages of using radix-2 and radix-4
butterflies.
The architecture has ceiling(log
power of four, all of the log
If transform length is not an integral power of four, the architecture implements
ceiling(log
remaining stage using a radix-2 architecture.
Each stage contains a single butterfly unit and a feedback delay unit. The feedback
delay unit delays the incoming data by a specified number of cycles; in each stage the
number of cycles of delay is one quarter of the number of cycles of delay in the
previous stage. The delays align the butterfly input samples correctly for the butterfly
calculations. The output of the pipeline is in index-reversed order.
For applications where transform time is to be minimized, a quad-output FFT engine
architecture is optimal. The term quad-output refers to the throughput of the internal
FFT butterfly processor. The engine implementation computes all four radix-4
butterfly complex outputs in a single clock cycle.
Figure 3–1
x[k,1]
x[k,2]
x[k,0]
x[k,3]
feedback unit unmodified through the butterfly unit to the next stage.
shows a diagram of the quad-output FFT engine.
4
(N)) – 1 of the stages in a radix-4 architecture, and implements the
-1
-1
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-1
j
-j
-1
j
G[k,0]
G[k,1]
G[k,2]
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4
(N) stages are implemented using a radix-4 architecture.
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4
FFT Engine
(N)) stages. If transform length is an integral
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2
H[k,0]
H[k,2]
H[k,3]
H[k,1]
FFT MegaCore Function User Guide
BFPU
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