IPR-FFT Altera, IPR-FFT Datasheet - Page 14

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–10
Table 1–14. Resource Usage with the Burst Data Flow Architecture—Stratix III Devices
Table 1–15. Performance with the Burst Data Flow Architecture—Stratix III Devices (Part 1 of 2)
FFT MegaCore Function User Guide
Notes to
(1) Represents data and twiddle factor precision.
(2) When using the burst data flow architecture, you can specify the number of engines in the FFT MegaWizard interface. You may choose from
Points
Points
1024
4096
1024
4096
1024
4096
1024
4096
1024
4096
1024
4096
1024
4096
1024
4096
1024
4096
256
256
256
256
256
256
256
256
256
one to two single-output engines in parallel, or from one, two, or four quad-output engines in parallel.
Table
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Single Output
Single Output
Single Output
Single Output
Single Output
Single Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Single Output
Single Output
Single Output
Architecture
Architecture
1–14:
Engine
Engine
Table 1–15
/2 adders complex multiplier structure, for data and twiddle width 16, for Stratix III
(EP3SE50F780C2) devices.
Number of
Engines
Engines
Number of
(1)
1
1
1
2
2
2
4
4
4
1
1
1
lists performance with burst data flow architecture, using the 4 multipliers
1
1
1
2
2
2
4
4
4
1
1
1
2
2
2
(2)
f
max
408
429
410
382
388
386
348
380
367
438
414
404
Combinational
(MHz)
ALUTs
1796
1830
1882
2968
3015
3054
5162
5213
5283
1037
1050
1092
704
740
805
Calculation Time
Cycles
24705
1069
5167
2607
1378
1115
5230
235
162
557
118
340
Transform
Registers
10100
10290
Logic
Time (μs)
3502
3686
3852
5489
5681
5856
9891
1435
1481
1527
2332
2408
2484
12.63
61.22
0.58
2.49
12.6
0.42
1.43
6.76
0.34
3.76
2.54
0.9
(2)
Memory
229632
229632
229632
147712
229632
Transform Calculation
14592
57600
14592
57600
14592
57600
37120
14592
57600
(Bits)
9472
Cycles
28801
2093
9263
1581
6703
1364
5474
1371
6344
491
397
374
Data Load &
Chapter 1: About This MegaCore Function
Memory
(M9K)
Time (μs)
© December 2010 Altera Corporation
28
15
15
28
28
28
28
19
11
28
Performance and Resource Utilization
22.59
17.39
14.92
15.31
71.37
8
8
3
6
9
4.87
1.04
4.07
1.07
3.59
3.13
1.2
18 × 18
Blocks
Cycles
Block Throughput
32898
1291
6157
1163
5133
1099
4633
1628
7279
12
12
12
24
24
24
48
48
48
331
299
283
4
4
4
8
8
8
(3)
Time (μs)
(MHz)
15.02
13.31
12.63
17.57
81.52
0.81
3.01
0.78
3.00
0.81
3.72
408
429
410
382
388
386
348
380
367
438
414
404
413
402
406
f
2.9
MAX