IPR-FFT Altera, IPR-FFT Datasheet - Page 7

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function
General Description
General Description
Fixed Transform Size Architecture
© December 2010 Altera Corporation
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For information about Avalon-ST interfaces, refer to the
The FFT MegaCore function is a high performance, highly-parameterizable Fast
Fourier transform (FFT) processor. The FFT MegaCore function implements a
complex FFT or inverse FFT (IFFT) for high-performance applications.
The FFT MegaCore function implements the following architectures:
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The fixed transform architecture FFT implements a radix-2/4 decimation-in-
frequency (DIF) FFT fixed-transform size algorithm for transform lengths of 2
6 ≤ m ≤ 16. This architecture uses block-floating point representations to achieve the
best trade-off between maximum signal-to-noise ratio (SNR) and minimum size
requirements.
The fixed transform architecture accepts as an input a two’s complement format
complex data vector of length N, where N is the desired transform length in natural
order; the function outputs the transform-domain complex vector in natural order. An
accumulated block exponent is output to indicate any data scaling that has occurred
during the transform to maintain precision and maximize the internal signal-to-noise
ratio. Transform direction is specifiable on a per-block basis via an input port.
Block floating-point architecture—maintains the maximum dynamic range of data
during processing (not for variable streaming)
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Avalon
Parameterization-specific VHDL and Verilog HDL testbench generation
Transform direction (FFT/IFFT) specifiable on a per-block basis
Easy-to-use IP Toolbench interface
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
DSP Builder ready
Fixed transform size architecture
Variable streaming architecture
Uses embedded memory
Maximum system clock frequency >300 MHz
Optimized to use Stratix series DSP blocks and TriMatrix™ memory
architecture
High throughput quad-output radix 4 FFT engine
Support for multiple single-output and quad-output engines in parallel
Multiple I/O data flow modes: streaming, buffered burst, and burst
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Streaming (Avalon-ST) compliant input and output interfaces
Avalon Interface
FFT MegaCore Function User Guide
Specifications.
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