IPR-FFT Altera, IPR-FFT Datasheet - Page 27

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
Set Up Simulation
© December 2010 Altera Corporation
f
c
7. Choose the complex multiplier implementation.
8. Turn on Global Clock Enable, if you want to add a global clock enable to your
9. Specify the memory options.
10. Click Finish when the implementation options are set.
For more information about the FFT MegaCore function parameters, refer to
on page
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
produced by the Quartus II software. The model allows for fast functional simulation
of IP using industry-standard VHDL and Verilog HDL simulators.
You may only use these simulation model output files for simulation purposes and
expressly not for synthesis or any other purposes. Using these models for synthesis
creates a nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow
these steps:
1. Click Step 2: Set Up Simulation in IP Toolbench
2. Turn on Generate Simulation Model
3. Choose the required language in the Language list.
You can choose a Structure with three multipliers and five adders or four
multipliers and two adders. You can also choose to Implement Multipliers in DSP
blocks only, logic cells only or both DSP blocks and logic cells. If your variable
streaming architecture FFT variation uses the floating point representation and
targets a Stratix V device, you can specify the multiplier type.
1
design.
You can set memory use balance with the Twiddle ROM Distribution, turn on
Use M-RAM Blocks, and turn on Implement appropriate logic functions in
RAM. If your FFT variation targets an appropriate device family, the Use M144K
Blocks option replaces the Use M-RAM Blocks option.
1
3–14.
The complex multiplier implementation options Structure and Implement
Multipliers in are not available for the variable streaming architecture. The
complex multiplier implementation option Multipliers is available only for
the variable streaming architecture using the floating point representation
in a Stratix V device.
The memory options are not available for the variable streaming
architecture. The memory options Twiddle ROM Distribution and Use
M-RAM Blocks are not available in the Cyclone series of device families
(the Cyclone, Cyclone II, Cyclone III,Cyclone III LS, and Cyclone IV device
families).
(Figure 2–7 on page
(Figure 2–3 on page
FFT MegaCore Function User Guide
2–8).
2–4).
Table 3–3
2–7