IPR-FFT Altera, IPR-FFT Datasheet - Page 37

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
The Avalon Streaming Interface
The Avalon Streaming Interface
© December 2010 Altera Corporation
Fixed point representation allows for natural word growth through the pipeline. The
maximum growth of each stage is log
design by growing the pipeline stages by either 2 bits or 3 bits. After the complex
multiplication the data is rounded down to the expanded data size using convergent
rounding.
The floating point internal data representation is single precision floating point
(32-bit, IEEE 754 representation). Floating point operations provide more precise
computation results but are costly in hardware resources. To reduce the amount of
logic required for floating point operations, the variable streaming FFT uses "fused"
floating point kernels. The reduction in logic occurs by fusing together several
floating point operations and reducing the number of normalizations that need to
occur.
You can select input and output orders generated by the FFT.
input and output order options.
Table 3–1. Input & Output Order Options
Some applications for the FFT require an FFT > user operation > IFFT chain. In this
case, choosing the input order and output order carefully can lead to significant
memory and latency savings. For example, consider where the input to the first FFT is
in natural order and the output is in bit-reversed order (FFT is operating in engine-
only mode). In this example, if the IFFT operation is configured to accept bit-reversed
inputs and produces natural order outputs (IFFT is operating in engine-only mode),
only the minimum amount of memory is required, which provides a saving of N
complex memory words, and a latency saving of N clock cycles, where N is the size of
the current transform.
The Avalon
modular protocol for data transfers from a source interface to a sink interface and
simplifies the process of controlling the flow of data in a datapath.
The Avalon-ST interface signals can describe traditional streaming interfaces
supporting a single stream of data without knowledge of channels or packet
boundaries. Such interfaces typically contain data, ready, and valid signals. The
Avalon-ST interface can also support more complex protocols for burst and packet
transfers with packets interleaved across multiple channels.
The Avalon-ST interface inherently synchronizes multi-channel designs, which allows
you to achieve efficient, time-multiplexed implementations without having to
implement complex control logic.
Natural
Bit reversed
DC-centered
Natural
Bit reversed
DC-centered
Input Order
®
Streaming (Avalon-ST) interface defines a standard, flexible, and
Bit reversed
Natural
Bit-reversed
Natural
Bit reversed
Natural
Output Order
Engine-only
Engine with
bit-reversal
Mode
2
(4 √2) = 2.5 bits, which is accommodated in the
Requires minimum memory and minimum latency.
At the output, requires an extra N complex memory
words and an additional N clock cycles latency,
where N is the size of the transform.
Comments
FFT MegaCore Function User Guide
Table 3–1
shows the
3–3