IPR-FFT Altera, IPR-FFT Datasheet - Page 13

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–12. Resource Usage with Buffered Burst Data Flow Architecture—Stratix III Devices
Table 1–13. Performance with the Buffered Burst Data Flow Architecture—Stratix III Devices
© December 2010 Altera Corporation
Note to
(1) When using the buffered burst architecture, you can specify the number of quad-output FFT engines in the FFT MegaWizard interface.
Notes to
(1) When using the buffered burst architecture, you can specify the number of quad-output engines in the FFT MegaWizard interface. You may
(2) In a buffered burst data flow architecture, transform time is defined as the time from when the N-sample input block is loaded until the first
(3) Block throughput is the minimum number of cycles between two successive start-of-packet (sink_sop) pulses.
Points
1024
4096
1024
4096
1024
4096
Points
256
256
256
1024
4096
1024
4096
1024
4096
256
256
256
choose from one, two, or four quad-output engines in parallel.
output sample is ready for output. Transform time does not include the additional N-1 clock cycle to unload the full output data block.
Table
Table
1–12:
Engines
1–13:
Number of
Engines
Number of
1
1
1
2
2
2
4
4
4
1
1
1
2
2
2
4
4
4
(1)
Table 1–12
multipliers /2 adders complex multiplier structure, for data and twiddle width 16, for
Stratix III (EP3SE50F780C2) devices.
Table 1–13
multipliers /2 adders complex multiplier structure, for data and twiddle width 16, for
Stratix III (EP3SE50F780C2) devices.
Table 1–14
multipliers /2 adders complex multiplier structure, for data and twiddle width 16, for
Stratix III (EP3SE50F780C2) devices.
(1)
Combinational
(MHz))
ALUTs
lists resource usage with buffered burst data flow architecture, using the 4
lists performance with buffered burst data flow architecture, using the 4
lists resource usage with burst data flow architecture, using the 4
1952
1989
2031
3261
3306
3348
5712
5775
5857
408
390
382
365
369
390
341
349
325
f
MAX
Transform Calculation
Cycles
1069
5167
2607
1378
235
162
118
340
557
Registers
Time
10195
10403
Logic
3586
3784
3968
5577
5785
5977
9971
(2)
Time (μs)
13.54
0.58
2.74
0.44
1.51
6.68
0.35
0.98
4.25
Memory
123136
491776
123136
491776
123136
491776
30976
30976
30976
(Bits)
Data Load & Transform
Cycles
2093
9263
1581
6703
1364
5474
491
397
347
Calculation
Memory
(M9K)
Time (μs)
16
16
60
31
31
60
60
60
60
24.27
17.17
16.87
5..37
1.09
4.29
1.02
3.91
1.2
FFT MegaCore Function User Guide
18 × 18
Blocks
12
12
12
24
24
24
48
48
48
Cycles
Block Throughput
6157
5133
4633
1291
1163
1099
331
299
283
(3)
Time (μs)
(MHz)
16.13
13.15
14.27
408
390
382
365
369
390
341
349
325
f
0.81
3.31
0.82
3.15
0.83
3.15
MAX
1–9