IPR-FFT Altera, IPR-FFT Datasheet - Page 34

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–14
Variable Streaming Architecture
Program a Device
FFT MegaCore Function User Guide
f
f
To compile your variable streaming architecture design, follow these steps:
1. If you are using the Quartus II software to synthesize your design, skip to step 2. If
2. On the Project menu, click Add/Remove Files in Project.
3. You should see a list of files in the project. If no files are listed, browse to the \lib
4. On the Processing menu, click Start Compilation.
After you have compiled your design, program your targeted Altera device, and
verify your design in hardware.
With Altera's free OpenCore Plus evaluation feature, you can evaluate the FFT
MegaCore function before you purchase a license. OpenCore Plus evaluation allows
you to generate an IP functional simulation model, and produce a time-limited
programming file.
For more information about IP functional simulation models, refer to the
Altera Designs
You can simulate the FFT in your design, and perform a time-limited evaluation of
your design in hardware.
For more information about OpenCore Plus hardware evaluation using the FFT, refer
to
Megafunctions.
“OpenCore Plus Evaluation” on page 1–14
you are using a third-party synthesis tool to synthesize your design, follow these
steps:
a. Set a black-box attribute for your FFT MegaCore function custom variation
b. Run the synthesis tool to produce an EDIF Netlist File (.edf) or Verilog Quartus
c. Add the EDIF or VQM file to your Quartus II project.
directory, then select and add all files with the prefix auk_dspip_r22sdf. Browse to
the <project> directory and select all files with prefix auk_dspip.
before you synthesize the design. Refer to Quartus II Help for instructions on
setting black-box attributes per synthesis tool.
Mapping (VQM) file (.vqm) for input to the Quartus II software.
chapter in volume 3 of the Quartus II Handbook.
and
AN 320: OpenCore Plus Evaluation of
© December 2010 Altera Corporation
Chapter 2: Getting Started
Program a Device
Simulating