IPR-FFT Altera, IPR-FFT Datasheet - Page 15

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–15. Performance with the Burst Data Flow Architecture—Stratix III Devices (Part 2 of 2)
Stratix IV Devices
Table 1–16. Performance with the Streaming Data Flow Engine Architecture—Stratix IV Devices
Table 1–17. Performance with the Variable Streaming Data Flow Engine Architecture—Stratix IV Devices
© December 2010 Altera Corporation
Notes to
(1) In the burst I/O data flow architecture, you can specify the number of engines in the FFT MegaWizard interface. You may choose from one to
(2) Transform time is the time frame when the input block is loaded until the first output sample (corresponding to the input block) is output.
(3) Block throughput is defined as the minimum number of cycles between two successive start-of-packet (sink_sop) pulses.
Point Type
Points
Points
1024
4096
Floating
Floating
Floating
1024
4096
256
256
Fixed
Fixed
Fixed
two single-output engines in parallel, or from one, two, or four quad-output engines in parallel.
Transform time does not include the time to unload the full output data block.
Table
Single Output
Single Output
Single Output
Architecture
Combinational
Points
1–15:
1024
4096
1024
4096
1
256
256
Engine
ALUTs
2092
2480
2356
Table 1–16
adders complex multiplier structure, for data and twiddle width 16, for Stratix IV
(EP4SGX70DF29C2X) devices.
Table 1–17
and bit-reversed outputs, for width 16 (32 for floating point), for Stratix IV
(EP4SGX70DF29C2X) devices.
The variable streaming with fixed-point number representation uses natural word
growth, therefore the multiplier requirement is larger compared with the equivalent
streaming FFT with the same number of points.
If you want to significantly reduce M9K memory utilization, set a lower f
Combinational
18024
14063
22030
ALUTs
Number of
2517
3489
4503
Engines
(1)
Registers
2
2
2
Logic
3714
4458
4545
shows the streaming data flow performance, using the 4 multipliers /2
shows the variable streaming data flow performance, with in order inputs
f
max
Registers
413
402
406
16714
13502
19806
Logic
4096
5433
6936
(MHz)
Memory
155904
622848
39,68
(Bits)
Calculation Time
Cycles
12329
2652
585
170639
140750
568579
10239
42218
34728
Bits
Transform
Memory
Memory
(M9K)
20
20
76
Time (μs)
30.34
1.42
6.6
M9K
146
10
15
33
61
89
(2)
18 × 18
Blocks
Transform Calculation
12
12
12
Cycles
16495
3676
841
18 × 18
Blocks
Data Load &
20
28
36
48
64
80
(MHz)
436
437
419
f
Time (μs)
MAX
40.59
(MHz)
2.04
9.15
323
329
327
320
314
310
f
FFT MegaCore Function User Guide
MAX
Count
Clock
Cycle
1024
4096
256
Count
Clock
Cycle
1024
4096
1024
4096
Cycles
256
256
Block Throughput
20605
1098
4701
MAX
Transform
(3)
Time (μs)
Transform
Time (μs)
Time (μs)
target.
0.59
2.34
9.78
12.52
13.23
0.79
3.12
3.26
11.71
50.71
0.8
2.66
1–11