IPR-FFT Altera, IPR-FFT Datasheet - Page 49

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Parameters
Table 3–3. Parameters (Part 2 of 3)
© December 2010 Altera Corporation
Structure
Implement Multipliers in
Multipliers (Stratix V)
Global clock enable
Twiddle ROM Distribution
Parameter
3 Mults/5 Adders
4 Mults/2 Adders
DSP Blocks/Logic Cells
Logic Cells Only
DSP Blocks Only
32×32 Multipliers
27×27 Multipliers
On or Off
100% M4K to 100%
M512 or 100% M9K to
100% MLAB
Value
You can implement the complex multiplier structure with four
real multipliers and two adders/subtracters, or three
multipliers, five adders, and some additional delay elements.
The 4 Mults/2 Adders structure uses the DSP block structures
to minimize logic usage, and maximize the DSP block usage.
This option may also improve the push button f
5 Mults/3 Adders structure requires fewer DSP blocks, but
more LEs to implement. It may also produce a design with a
lower f
in Stratix V devices.
Each real multiplication can be implemented in DSP blocks or
LEs only, or using a combination of both. If you use a
combination of DSP blocks and LEs, the FFT MegaCore
function automatically extends the DSP block 18 × 18
multiplier resources with LEs as needed. Not available for
variable streaming architecture or in Stratix V devices.
This option is available only for the variable streaming
architecture using floating point representation in Stratix V
devices. You can implement the complex multiplier structure
using 32×32 multipliers for better accuracy or using 27×27
multipliers for better DSP resource utilization.
Turn on if you want to add a global clock enable to your design.
High-throughput FFT parameterizations can require multiple
shallow ROMs for twiddle factor storage. If your target device
family supports M512 RAM blocks (or MLAB blocks in Stratix
III, Stratix IV, and Stratix V devices), you can choose to
distribute the ROM storage requirement between M4K (M9K in
Stratix III and Stratix IV devices) RAM and M512 (MLAB) RAM
blocks by adjusting the slider bar. Set the slider bar to the far
left to implement the ROM storage completely in M4K (M9K)
RAM blocks; set the slider bar to the far right to implement the
ROM completely in M512 (MLAB) RAM blocks. In Stratix V
devices, replace M4K (M9K) with M20K memory blocks.
Implementing twiddle ROM in M512 (MLAB) RAM blocks can
lead to a more efficient device internal memory bit usage.
Alternatively, this option can be used to conserve M4K (M9K)
RAM blocks used for the storage of FFT data or other storage
requirements in your system.
Not available for variable streaming architecture or in the
Cyclone series of device families.
MAX
. Not available for variable streaming architecture or
Description
FFT MegaCore Function User Guide
MAX
. The
3–15