IPR-FFT Altera, IPR-FFT Datasheet - Page 33

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Compile the Design
Compile the Design
Fixed Transform Architecture
© December 2010 Altera Corporation
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For more information about NativeLink, refer to the
Simulation Tools
You can use the Tcl script file <variation name>_nativelink.tcl to assign default
NativeLink testbench settings to the Quartus II project.
To set up simulation in the Quartus II software using NativeLink, follow these steps:
1. Create a custom variation but ensure you specify your variation name to match the
2. Check that the absolute path to your third-party simulator executable is set. On the
3. On the Processing menu, point to Start and click Start Analysis & Elaboration.
4. On the Tools menu, click Tcl scripts. Select the <variation name>_nativelink.tcl Tcl
5. On the Assignments menu, click Settings, expand EDA Tool Settings and select
6. On the Tools menu, point to EDA Simulation Tool and click Run EDA RTL
Use the Quartus II software to synthesize and place and route your design. Refer to
Quartus II Help for instructions on performing compilation.
To compile your fixed-transform architecture design, follow these steps:
1. If you are using the Quartus II software to synthesize your design, skip to step 2. If
The .qip file supersedes the files you had to add to the project explicitly in previous
versions of the Quartus II software. The .qip file contains the information about the
MegaCore function that the Quartus II software requires.
2. On the Processing menu, click Start Compilation.
Quartus II project name.
Tools menu click Options and select EDA Tools Options.
script and click Run. Check for a message confirming that the Tcl script was
successfully loaded.
Simulation. Select a simulator under Tool Name and in NativeLink Settings,
select Test Benches.
Simulation.
you are using a third-party synthesis tool to synthesize your design, follow these
steps:
a. Set a black box attribute for your FFT MegaCore function custom variation
b. Run the synthesis tool to produce an EDIF Netlist File (.edf) or Verilog Quartus
c. Add the EDIF or VQM file to your Quartus II project.
before you synthesize the design. Refer to Quartus II Help for instructions on
setting black-box attributes per synthesis tool.
Mapping (VQM) file (.vqm) for input to the Quartus II software.
chapter in volume 3 of the Quartus II Handbook.
Simulating Altera IP in Third-Party
FFT MegaCore Function User Guide
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