IPR-FFT Altera, IPR-FFT Datasheet - Page 41

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
I/O Data Flow Architectures
Streaming
© December 2010 Altera Corporation
f
The streaming I/O data flow FFT architecture allows continuous processing of input
data, and outputs a continuous complex data stream without the requirement to halt
the data flow in or out of the FFT function.
Streaming FFT Operation
Figure 3–3 on page 3–7
Following the de-assertion of the system reset, the data source asserts sink_valid to
indicate to the FFT function that valid data is available for input. A successful data
transfer occurs when both the sink_valid and the sink_ready are asserted.
When the data transfer is complete, sink_sop is de-asserted and the data samples
are loaded in natural order.
For more information about the signals, refer to
For more information about the Avalon-ST interface, refer to the
Specifications.
Figure 3–3. FFT Streaming Data Flow Architecture Simulation Waveform
Figure 3–4
asserts sink_eop and sink_valid for the last data transfer.
Figure 3–4. FFT Streaming Data Flow Architecture Input Flow Control
sink_ready
sink_imag
sink_valid
sink_real
sink_sop
reset_n
inverse
source_ready
source_imag
source_valid
source_real
source_sop
source_eop
source_exp
sink_ready
sink_imag
sink_valid
clk
shows the input flow control. When the final sample is loaded, the source
sink_eop
sink_real
sink_sop
reset_n
inverse
clk
shows an example simulation waveform.
EXP0
x r (0)
x i (0)
Table 3–4 on page
x r (1) x r (2) x r (3) x r (4) x r (5) x r (6) x r (7)
x i (1) x i (2) x i (3)
EXP1
FFT MegaCore Function User Guide
EXP2
x i (4) x i (5) x i (6)
Avalon Interface
3–16.
EXP3
x i (7)
3–7