IPR-FFT Altera, IPR-FFT Datasheet - Page 48

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–14
Table 3–3. Parameters (Part 1 of 3)
FFT MegaCore Function User Guide
Target Device Family
Transform Length
Data Precision
Twiddle Precision
FFT Engine Architecture
Number of Parallel FFT Engines 1, 2, 4
I/O Data Flow
I/O Order
Data Representation
Parameter
<device family>
64, 128, 256, 512,
1024, 2048, 4096,
8192, 16384, 32768, or
65536. Variable
streaming also allows
16, 32, 131072, and
262144.
8, 10, 12, 14, 16, 18,
20, 24, 28, 32
8, 10, 12, 14, 16, 18,
20, 24, 28, 32
Quad Output,
Single Output
Streaming
Variable Streaming
Buffered Burst
Burst
Bit Reverse Order,
Natural Order,
–N/2 to N/2
Fixed Point or Floating
Point
Value
Displays the target device family. The device family is normally
preselected by the project specified in the Quartus II software.
The generated HDL for your MegaCore function variation may
be incorrect if this value does not match the value specified in
the Quartus II project.
The device family must be the same as your Quartus II project
device family.
The transform length. For variable streaming, this value is the
maximum FFT length.
The data precision. The values 28 and 32 are available for
variable streaming only.
The twiddle precision. The values 28 and 32 are available for
variable streaming only. Twiddle factor precision must be less
than or equal to data precision.
For both the Buffered Burst and Burst I/O data flow
architectures, you can choose between one, two, and four
quad-output FFT engines working in parallel. Alternatively, if
you have selected a single-output FFT engine architecture, you
may choose to implement one or two engines in parallel.
Multiple parallel engines reduce the FFT MegaCore function’s
transform time at the expense of device resources—which
allows you to select the desired area and throughput trade-off
point.
For more information about device resource and transform
time trade-offs, refer to
available for variable streaming or streaming architecture.
Choose the FFT architecture.
The input and output order for data entering and leaving the
FFT (variable streaming architecture only).
The internal data representation type (variable streaming
architecture only), either fixed point with natural bit-growth or
single precision floating point.
““Parameters” on page
Description
© December 2010 Altera Corporation
Chapter 3: Functional Description
3–13. Not
Parameters