IPR-FFT Altera, IPR-FFT Datasheet - Page 38

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–4
FFT Processor Engine Architectures
Radix-2
FFT MegaCore Function User Guide
2
Single Delay Feedback Architecture
f
The Avalon-ST interface supports backpressure, which is a flow control mechanism in
which a sink can signal to a source to stop sending data. The sink typically uses
backpressure to stop the flow of data when its FIFO buffers are full or when there is
congestion on its output. When designing a datapath, which includes the FFT
MegaCore function, you may not need backpressure if you know the downstream
components can always receive data. You may achieve a higher clock rate by driving
the source ready signal source_ready of the FFT high, and not connecting the sink
ready signal sink_ready.
The FFT MegaCore function has a READY_LATENCY value of zero.
For more information about the Avalon-ST interface, refer to the
Specifications.
The FFT MegaCore function can be parameterized to use either quad-output or
single-output engine architecture. To increase the overall throughput of the FFT
MegaCore function, you may also use multiple parallel engines of a variation. This
section discusses the following topics:
■
■
■
■
Radix-2
calculating the FFT of incoming data. It is similar to radix-2 single delay feedback
architectures. However, the twiddle factors are rearranged such that the
multiplicative complexity is equivalent to a radix-4 single delay feedback architecture.
There are log
feedback delay unit that delays the incoming data by a specified number of cycles,
halved at every stage. These delays effectively align the correct samples at the input of
the butterfly unit for the butterfly calculations. Every second stage contains a
modified radix-2 butterfly whereby a trivial multiplication by –j is performed before
the radix-2 butterfly operations. The output of the pipeline is in bit-reversed order.
The following scheduled operations occur in the pipeline for an FFT of length N = 16.
1. For the first 8 clock cycles, the samples are fed unmodified through the butterfly
2. The next 8 clock cycles perform the butterfly calculation using the data from the
Radix 2
variations
Mixed radix-4/2 architecture for floating point variable streaming variations
Quad-output FFT engine architecture for streaming, buffered burst, and burst
variations
Single-output FFT engine architecture for buffered burst and burst variations
unit to the delay feedback unit.
delay feedback unit and the incoming data. The higher order calculations are sent
through to the delay feedback unit while the lower order calculations are sent to
the next stage.
2
single delay feedback architecture is a fully pipelined architecture for
2
single-delay feedback architecture for fixed-point variable streaming
2
(N) stages with each stage containing a single butterfly unit and a
© December 2010 Altera Corporation
Chapter 3: Functional Description
FFT Processor Engine Architectures
Avalon Interface