IPR-FFT Altera, IPR-FFT Datasheet - Page 40

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–6
Single-Output FFT Engine Architecture
Figure 3–2. Single-Output FFT Engine Architecture
I/O Data Flow Architectures
FFT MegaCore Function User Guide
RAM
f
Complex data samples x[k,m] are read from internal memory in parallel and re-
ordered by switch (SW). Next, the ordered samples are processed by the radix-4
butterfly processor to form the complex outputs G[k,m]. Because of the inherent
mathematics of the radix-4 DIF decomposition, only three complex multipliers are
required to perform the three non-trivial twiddle-factor multiplications on the outputs
of the butterfly processor. To discern the maximum dynamic range of the samples, the
four outputs are evaluated in parallel by the block-floating point units (BFPU). The
appropriate LSBs are discarded and the complex values are rounded and re-ordered
before being written back to internal memory.
For applications where the minimum-size FFT function is desired, a single-output
engine is most suitable. The term single-output again refers to the throughput of the
internal FFT butterfly processor. In the engine architecture, a single butterfly output is
computed per clock cycle, requiring a single complex multiplier
page
This section describes and illustrates the following I/O data flow architectural
options supported by the FFT MegaCore function:
■
■
■
■
For information about setting the architectural parameters in IP Toolbench, refer to
“Parameterize the MegaCore Function” on page
Streaming
Variable Streaming
Buffered Burst
Burst
x[k,0]
x[k,3]
x[k,1]
x[k,2]
3–6).
-1
-1
-1
-j
j
-j
-1
j
G[k,0]
G[k,1]
G[k,2]
G[k,3]
FFT Engine
2–3.
ROM
H[k,m]
© December 2010 Altera Corporation
Chapter 3: Functional Description
(Figure 3–2 on
I/O Data Flow Architectures
BFPU
RAM