IPR-FFT Altera, IPR-FFT Datasheet - Page 55

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Appendix A: Block Floating Point Scaling
Implementing Scaling
© December 2010 Altera Corporation
2. Map the output data to the appropriate location within the expanded dynamic
3. Sign extend the data within the full scale register.
A sample of Verilog HDL code that illustrates the scaling of the output data (for
exponents –11 to –9) with sign extension is shown in the following example:
In this example, the output provides a full scale 27-bit word. You need to choose how
many and which bits should be carried forward in the processing chain. The choice of
bits determines the absolute gain relative to the input sample level.
Figure A–1 on page A–4
the 256-point quad output FFT with an input signal level of 5000H. The output of the
FFT is 280H when the exponent = –5. The figure illustrates all cases of valid exponent
values of scaling to the full scale storage register [26..0]. Since the exponent is –5, you
need to look at the register values for that column. This data is shown in the last two
columns in the figure. Note that the last column represents the gain compensated data
after the scaling (0005000H), which agrees with the input data as expected. If you
want to keep 16 bits for subsequent processing, you can choose the bottom 16 bits that
result in 5000H. However, if you choose a different bit range, such as the top 16 bits,
the result is 000AH. Therefore, the choice of bits affects the relative gain through the
processing chain.
Because this example has 27 bits of full scale resolution and 16 bits of output
resolution, choose the bottom 16 bits to maintain unity gain relative to the input
signal. Choosing the LSBs is not the only solution or the correct one for all cases. The
choice depends on which signal levels are important. One way to empirically select
the proper range is by simulating test cases that implement expected system data. The
output of the simulations should tell what range of bits to use as the output register. If
the full scale data is not used (or just the MSBs), you must saturate the data to avoid
wraparound problems.
range register based upon the exponent value. To continue the above example, the
16-bit output data [15..0] from the FFT/IFFT is mapped to [26..11] for an exponent
of –11, to [25..10] for an exponent of –10, to [24..9] for an exponent of –9, and so on.
case (exp)
endcase
6'b110101 : //-11 Set data equal to MSBs
6'b110110 : //-10 Equals left shift by 10 with sign extension
6'b110111 : //-9 Equals left shift by 9 with sign extension
.
.
.
begin
end
begin
end
begin
end
full_range_real_out[26:0] <= {real_in[15:0],11'b0};
full_range_imag_out[26:0] <= {imag_in[15:0],11'b0};
full_range_real_out[26] <= {real_in[15]};
full_range_real_out[25:0] <= {real_in[15:0],10'b0};
full_range_imag_out[26] <= {imag_in[15]};
full_range_imag_out[25:0] <= {imag_in[15:0],10'b0};
full_range_real_out[26:25] <= {real_in[15],real_in[15]};
full_range_real_out[24:0] <= {real_in[15:0],9'b0};
full_range_imag_out[26:25] <= {imag_in[15],imag_in[15]};
full_range_imag_out[24:0] <= {imag_in[15:0],9'b0};
demonstrates the effect of scaling for all possible values for
FFT MegaCore Function User Guide
A–3