IPR-FFT Altera, IPR-FFT Datasheet - Page 8

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–4
Variable Streaming Architecture
MegaCore Verification
Performance and Resource Utilization
Cyclone III Devices
FFT MegaCore Function User Guide
f
1
The variable streaming architecture FFT implements two different types of
architecture. The variable streaming FFT variations implement either a radix-2
delay feedback architecture, using a fixed-point representation, or a mixed radix-4/2
architecture, using a single precision floating point representation. After you select
your architecture type, you can configure your FFT variation during runtime to
perform the FFT algorithm for transform lengths of 2
The fixed-point representation grows the data widths naturally from input through to
output thereby maintaining a high SNR at the output. The single precision floating
point representation allows a large dynamic range of values to be represented while
maintaining a high SNR at the output.
For more information about radix-2
and M. Torkelson, A New Approach to Pipeline FFT Processor, Department of Applied
Electronics, Lund University, IPPS 1996.
The order of the input data vector of size N can be natural, bit reversed, or –N/2 to
N/2 (DC-centered). The architecture outputs the transform-domain complex vector in
natural or bit-reversed order. The transform direction is specifiable on a per-block
basis using an input port.
Before releasing a version of the FFT MegaCore function, Altera runs comprehensive
regression tests to verify its quality and correctness.
Custom variations of the FFT MegaCore function are generated to exercise its various
parameter options, and the resulting simulation models are thoroughly simulated
with the results verified against master simulation models.
Performance varies depending on the FFT engine architecture and I/O data flow. All
data represents the geometric mean of a three seed Quartus II synthesis sweep.
Cyclone III devices use combinational look-up tables (LUTs) and logic registers;
Stratix III devices use combinational adaptive look-up tables (ALUTs) and logic
registers.
Table 1–4
adders complex multiplier structure, for width 16, for Cyclone III (EP3C10F256C6)
devices.
shows the streaming data flow performance, using the 4 multipliers / 2
2
single delay feedback architecture, refer to S. He
m
Chapter 1: About This MegaCore Function
where 4 ≤ m ≤ 18.
© December 2010 Altera Corporation
MegaCore Verification
2
single