ADV7183BBSTZ Analog Devices Inc, ADV7183BBSTZ Datasheet - Page 12

• Manufacturer Part Number: ADV7183BBSTZ
• Description: IC,TV/VIDEO CIRCUIT,Color Decoder Circuit,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7183BBSTZ

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7183B
Table 7. Pin Function Descriptions
Pin No.
3, 9, 14, 31, 71
39, 40, 47, 53, 56
4, 15
10, 30, 72
50
38
42, 44, 46, 58, 60,
62, 41, 43, 45, 57,
59, 61
11
13, 16 to 18, 25, 34,
35, 63, 65, 69, 70,
77, 78
33, 32, 24, 23, 22,
21, 20, 19, 8, 7, 6, 5,
76, 75, 74, 73
2
1
80
67
68
66
64
27
26
29
28
36
79
37
12
51
52
48, 49
54, 55
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
AIN1 to AIN12
INTRQ
NC
P0 to P15
HS
VS
FIELD
SDA
SCLK
ALSB
RESET
LLC1
LLC2
XTAL
XTAL1
PWRDN
OE
ELPF
SFL
REFOUT
CML
CAPY1, CAPY2
CAPC1, CAPC2
I
O
Type
G
G
P
P
P
P
O
O
O
O
I/O
I
I
I
O
O
I
O
I
I
I
O
O
O
I
I
Description
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video. See the interrupt register map in
No Connect Pins.
Video Pixel Output Port.
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
I
I
This pin selects the I
write as 0x40; for ALSB set to logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7183B circuitry.
This is a line-locked output clock for the pixel data output by the ADV7183B. Nominally
27 MHz, but varies up or down according to video line length.
This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the
ADV7183B. Nominally 13.5 MHz, but varies up or down according to video line length.
This is the input pin for the 28.6363 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an
external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7183B. In crystal
mode, the crystal must be a fundamental crystal.
A logic low on this pin places the ADV7183B in a power-down mode. Refer to the
Register Maps section for more options on power-down modes for the ADV7183B.
When set to a logic low, OE enables the pixel output bus, P15 to P0 of the ADV7183B. A
logic high on the OE pin places Pins P15 to P0, HS, VS, SFL into a high impedance state.
The recommended external loop filter must be connected to this ELPF pin, as shown in
F igure 46.
1 3 5 H
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital
video encoder.
Internal Voltage Reference Output. Refer to
for this pin.
The CML pin is a common-mode level for the internal ADCs. Refer to
recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to
this pin.
ADC’s Capacitor Network. Refer to
this pin.
2
2
C Port Serial Data Input/Output Pin.
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
Rev. B | Page 12 of 100
2
C address for the ADV7183B. ALSB set to Logic 0 sets the address for a
F igure 46 for a recommended capacitor network for
1 3 8 H
F igure 46 for a recommended capacitor network for
1 3 9 H
T able 83.
1 3 3 H
F igure 46 for a recommended capacitor network
1 3 6 H
F igure 46 for a
1 3 7 H
I P2PC
1 3 4 H