ADV7183BBSTZ Analog Devices Inc, ADV7183BBSTZ Datasheet - Page 39

• Manufacturer Part Number: ADV7183BBSTZ
• Description: IC,TV/VIDEO CIRCUIT,Color Decoder Circuit,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7183BBSTZ

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SYNCHRONIZATION OUTPUT SIGNALS
HS Configuration
The following controls allow the user to configure the behavior
of the HS output pin only:
•
•
•
The HS begin and HS end registers allow the user to freely
position the HS output (pin) within the video line. The values
in HSB[10:0] and HSE[10:0] are measured in pixel units from
the falling edge of HS. Using both values, the user can program
both the position and length of the HS output signal.
HSB[10:0] HS Begin, Address 0x34[6:4], Address
0x35[7:0]
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see
00000000010b, which is 2 LLC1 clock cycles from Count[0].
The default value of HSB[10:0] is 0x002, indicating the HS pulse
starts two pixels after the falling edge of HS.
Table 55. HS Timing Parameters (see
Standard
NTSC
NTSC Square Pixel
PAL
Beginning of HS signal via HSB[10:0]
End of HS signal via HSE[10:0]
Polarity of HS using PHS
PIXEL
LLC1
BUS
HS
ACTIVE
VIDEO
Cr
D
E
Y
HS Begin Adjust
(HSB[10:0])
(Default)
00000000010b
00000000010b
00000000010b
FF
00
4 LLC1
EAV
HSE[10:0]
00
F igure 20). HSB is set to
2 0 5 H
XY
F igure 20)
2 0 7 H
80
HS End Adjust
(HSE[10:0]) (Default)
00000000000b
00000000000b
00000000000b
10
HSB[10:0]
80
10
H BLANK
80
Rev. B | Page 39 of 100
Figure 20. HS Timing
10
C
HS to Active Video
(LLC1 Clock Cycles)
(C in
272
276
284
F igure 20) (Default)
2 0 8 H
Characteristic
HSE[10:0] HS End, Address 0x34[2:0], Address 0x36[7:0]
The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see
00000000000b, which is 0 LLC1 clock cycles from Count[0].
The default value of HSE[9:0] is 000, indicating that the HS
pulse ends zero pixels after falling edge of HS.
For example:
1.
2.
To move 20 LLC1s away from active video is equal to
subtracting 20 from 1716 and adding the result in binary to
both HSB[10:0] and HSE[10:0].
PHS Polarity HS, Address 0x37[7]
The polarity of the HS pin can be inverted using the PHS bit.
When PHS is 0 (default), HS is active high.
When PHS is 1, HS is active low.
FF
E
To shift the HS toward active video by 20 LLC1s, add
20 LLC1s to both HSB and HSE, that is, HSB[10:0] =
[00000010110], HSE[10:0] = 00000010100].
To shift the HS away from active video by 20 LLC1s, add
1696 LLC1s to both HSB and HSE (for NTSC), that is,
HSB[10:0] = [11010100010], HSE[10:0] = [11010100000].
1696 is derived from the NTSC total number of pixels =
1716.
00
SAV
00
XY
Cb
Active Video
Samples/Line
(D in
720Y + 720C = 1440
640Y + 640C = 1280
720Y + 720C = 1440
Y
Cr
F igure 20)
2 0 9 H
ACTIVE VIDEO
Y
F igure 20). HSE is set to
2 0 6 H
D
Cb
Y
Cr
Total LLC1
Clock Cycles
(E in
1716
1560
1728
ADV7183B
F igure 20)
2 1 0 H