ADV7183BBSTZ Analog Devices Inc, ADV7183BBSTZ Datasheet - Page 58

• Manufacturer Part Number: ADV7183BBSTZ
• Description: IC,TV/VIDEO CIRCUIT,Color Decoder Circuit,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7183BBSTZ

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7183B
Interrupt Request Output Operation
When an interrupt event occurs, the interrupt pin INTRQ
goes low with a programmable duration given by
INTRQ_DUR_SEL[1:0]
INTRQ_DURSEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space)[7:6]
Table 76. INTRQ_DUR_SEL
INTRQ_DURSEL[1:0]
00 (default)
01
10
11
When the active until cleared interrupt duration is selected and
the event that caused the interrupt is no longer in force, the
interrupt persists until it is masked or cleared.
For example, if the ADV7183B loses lock, an interrupt is
generated and INTRQ pin goes low. If the ADV7183B returns
to the locked state, INTRQ continues to drive low until the
SD_LOCK bit is either masked or cleared.
Interrupt Drive Level
The ADV7183B resets with open drain enabled and all
interrupts masked off. Therefore, INTRQ is in a high
impedance state after reset. 01 or 10 has to be written to
INTRQ_OP_SEL[1:0] for a logic level to be driven out from the
INTRQ pin.
It is also possible to write to a register in the ADV7183B that
manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ.
Description
3 Xtal periods
15 Xtal periods
63 Xtal periods
Active until cleared
Rev. B | Page 58 of 100
INTRQ_OP_SEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space)[1:0]
Table 77. INTRQ_OP_SEL
INTRQ_OP_SEL[1:0]
00 (default)
01
10
11
Multiple Interrupt Events
If Interrupt Event 1 occurs and then Interrupt Event 2 occurs
before the system controller has cleared or masked Interrupt
Event 1, the ADV7183B will not generate a second interrupt
signal. The system controller should check all unmasked
interrupt status bits, as more than one can be active.
Macrovision Interrupt Selection Bits
The user can select between pseudo sync pulse and color stripe
detection as shown in this section.
MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection
Bits Address 0x40 (Interrupt Space)[5:4]
Table 78. MV_INTRQ_SEL
MV_INTRQ_SEL[1:0]
00
01 (default)
10
11
Additional information relating to the interrupt system is
detailed in
T able 84.
2 5 5 H
Open drain
Drive low when active
Description
Drive high when active
Reserved
Description
Reserved
Pseudo sync only
Color stripe only
Either pseudo sync or color stripe