ADV7183BBSTZ Analog Devices Inc, ADV7183BBSTZ Datasheet - Page 30

• Manufacturer Part Number: ADV7183BBSTZ
• Description: IC,TV/VIDEO CIRCUIT,Color Decoder Circuit,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7183BBSTZ

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7183B
CSFM[2:0] C- Shaping Filter Mode, Address 0x17[7]
The C-shaping filter mode bits allow the user to select from a
range of low-pass filters, SH1 to SH5 and wideband mode for
the chrominance signal. The autoselection options automa-
tically select from the filter options to give the specified
response. (See settings 000 and 001 in
Table 32. CSFM Function
CSFM[2:0]
000 (default)
001
010
011
100
101
110
111
F igure 16 shows the responses of SH1 (narrowest) to SH5
1 8 5 H
(widest) and the wide band mode (in red).
–10
–20
–30
–40
–50
–60
0
0
Figure 16. Chroma Shaping Filter Responses
1
COMBINED C ANTIALIAS, C SHAPING FILTER,
Description
Autoselect 1.5 MHz bandwidth
Autoselect 2.17 MHz bandwidth
SH1
SH2
SH3
SH4
SH5
Wideband mode
2
MINIMUM
VOLTAGE
FREQUENCY (MHz)
C RESAMPLER
MAXIMUM
VOLTAGE
3
4
T able 32).
1 8 4 H
CLAMP
LEVEL
5
6
Figure 17. Gain Control Overview
Rev. B | Page 30 of 100
ANALOG VOLTAGE
RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7189B)
ADC
GAIN OPERATION
The gain control within the ADV7183B is performed strictly on
a digital basis. The input ADCs support a 10-bit range, mapped
into a 1.6 V analog voltage range. Gain correction occurs after
the digitization in the form of a digital multiplier.
One advantage of this architecture over the commonly used
programmable gain amplifier (PGA) before the ADCs is that
the gain is now completely independent of supply, temperature,
and process variations.
As shown in
signal providing it fits into the ADC window. Two components
to this are the amplitude of the input signal and the dc level on
which it resides. The dc level is set by the clamping circuitry
(see the
If the amplitude of the analog video signal is too high, clipping
can occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.
The minimum supported amplitude of the input video is
determined by the ADV7183B’s ability to retrieve horizontal
and vertical timing and to lock to the color burst, if present.
There are two gain control units, one each for luma and chroma
data. Both can operate independently of each other. The
chroma unit, however, can also take its gain value from the
luma path.
The possible AGC modes are summarized in
It is possible to freeze the automatic gain control loops. This
causes the loops to stop updating and the AGC determined
gain, at the time of the freeze, to stay active. The ACG
determined gain stays active until the automatic gain control
loop is either unfrozen, or the gain mode of the operation is
changed.
The currently active gain from any of the modes can be read
back. Refer to the description of the dual function manual gain
registers, LG[11:0] Luma Gain and CG[11:0] Chroma Gain, in
the
PROCESSOR
L uma Gain and
1 8 9 H
DATA
(DPP)
PRE-
C lamp Operation section).
1 8 7 H
F igure 17, the ADV7183B can decode a video
1 8 6 H
SDP
(GAIN SELECTION ONLY)
C hroma Gain sections.
1 9 0 H
CONTROL
GAIN
T able 33.
1 8 8 H