ADV7183BBSTZ Analog Devices Inc, ADV7183BBSTZ Datasheet - Page 59

• Manufacturer Part Number: ADV7183BBSTZ
• Description: IC,TV/VIDEO CIRCUIT,Color Decoder Circuit,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7183BBSTZ

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIXEL PORT CONFIGURATION
The ADV7183B has a very flexible pixel port that can be confi-
gured in a variety of formats to accommodate downstream ICs.
T able 79 and
2 5 6 H
ADV7183B’s pins can have in different modes of operation.
The ordering of components (for example, Cr versus Cb,
CHA/B/C) can be changed. Refer to the section.
indicates the default positions for the Cr/Cb components.
OF_SEL[3:0] Output Format Selection, Address 0x03[5:2]
The modes in which the ADV7183B pixel port can be onfigured
are under the control of OF_SEL[3:0]. See
The default LLC frequency output on the LLC1 pin is
approximately 27 MHz. For modes that operate with a nominal
data rate of 13.5 MHz (0001, 0010), the clock frequency on the
LLC1 pin stays at the higher rate of 27 MHz. For information
on outputting the nominal 13.5 MHz clock on the LLC1 pin, see
the
Table 79. P15 to P0 Output/Input Pin Mapping
Format, and Mode
Video Out, 8-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
Table 80. Standard Definition Pixel Port Modes
OF_SEL[3:0]
0010
0011 (default)
0110-1111
P AD_SEL[2:0], Address 0x8F[6:4] section.
2 6 0 H
T able 80 summarize the various functions that the
2 5 7 H
Format
16-bit @ LLC2 4:2:2
8-bit @ LLC1 4:2:2 (default)
Reserved
15
T able 80 for details.
2 5 9 H
14
T able 79
2 5 8 H
13
YCrCb[7:0] OUT
Y[7:0] OUT
12
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11
SWPC Swap Pixel Cr/Cb, Address 0x27[7]
This bit allows Cr and Cb samples to be swapped.
When SWPC is 0 (default), no swapping is allowed.
When SWPC is 1, the Cr and Cb values can be swapped.
PAD_SEL[2:0], Address 0x8F[6:4]
This I
(nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).
The LLC2 signal is useful for LLC2-compatible wide bus
(16-bit) output modes. See the
Selection, Address 0x03[5:2] section for additional information.
The LLC2 signal and data on the data bus are synchronized. By
default, the rising edge of LLC1/LLC2 is aligned with the Y
data; the falling edge occurs when the data bus holds C data.
The polarity of the clock, and therefore the Y/C assignments to
the clock edges, can be altered by using the Polarity LLC pin.
When LLC_PAD_SEL[2:0] is 000 (default), the output is
nominally 27 MHz LLC on the LLC1 pin.
When LLC_PAD_SEL[2:0] is 101, the output is nominally
13.5 MHz LLC on the LLC1 pin.
10
Data Port Pins P[15:0]
P[15:8]
Y[7:0]
YCrCb[7:0] (default)
2
C write allows the user to select between the LLC1
9
8
7
Reserved. Do not use.
6
P[15: 0]
O F_SEL[3:0] Output Format
2 6 1 H
5
CrCb[7:0] OUT
4
P[7: 0]
CrCb[7:0]
Three-state
3
ADV7183B
2
1
0