ADV7183BBSTZ Analog Devices Inc, ADV7183BBSTZ Datasheet - Page 42

IC,TV/VIDEO CIRCUIT,Color Decoder Circuit,CMOS,QFP,80PIN,PLASTIC

ADV7183BBSTZ

Manufacturer Part Number
ADV7183BBSTZ
Description
IC,TV/VIDEO CIRCUIT,Color Decoder Circuit,CMOS,QFP,80PIN,PLASTIC
Manufacturer
Analog Devices Inc
Type
Video Decoderr
Datasheet

Specifications of ADV7183BBSTZ

Applications
Projectors, Recorders, Security
Voltage - Supply, Analog
3.15 V ~ 3.45 V
Voltage - Supply, Digital
1.65 V ~ 2 V
Mounting Type
Surface Mount
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ADV7183B
Table 56. Recommended User Settings for NTSC (See
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE5
0xE6
0xE7
NOT VALID FOR USER
PROGRAMMING
VSYNC BY NVBEG[4:0]
ADVANCE BEGIN OF
ADVANCE BY
NVBEGDELO
ADDITIONAL
DELAY BY
0.5 LINE
VSBHO
1 LINE
YES
1
1
Figure 23. NTSC Vsync Begin
1
VSYNC BEGIN
0
0
NVBEGSIGN
ODD FIELD?
0
0
VSYNC BY NVBEG[4:0]
DELAY BEGIN OF
ADVANCE BY
NVBEGDELE
ADDITIONAL
Register Name
Vsync Field Control 1
Vsync Field Control 2
Vsync Field Control 3
Hsync Pos. Control 1
Hsync Pos. Control 2
Hsync Pos. Control 3
Polarity
NTSV_V_Bit_Beg
NTSC_V_Bit_End
NTSC_F_Bit_Tog
DELAY BY
0
0.5 LINE
VSBHE
1 LINE
NO
1
1
F igure 22)
2 1 8 H
Rev. B | Page 42 of 100
NVBEGDELO NTSC Vsync Begin Delay on Odd Field,
Address 0xE5[7]
When NVBEGDELO is 0 (default), there is no delay.
Setting NVBEGDELO to 1, delay Vsync going high on an odd
field by a line relative to NVBEG.
NVBEGDELE NTSC Vsync Begin Delay on Even Field,
Address 0xE5[6]
When NVBEGDELE is 0 (default), there is no delay.
Setting NVBEGDELE to 1 delays Vsync going high on an even
field by a line relative to NVBEG.
NVBEGSIGN NTSC Vsync Begin Sign, Address 0xE5[5]
Setting NVBEGSIGN to 0 delays the start of Vsync. Set for user
manual programming.
Setting NVBEGSIGN to 1 (default), advances the start of Vsync.
Not recommended for user programming.
NVBEG[4:0] NTSC Vsync Begin, Address 0xE5[4:0]
The default value of NVBEG is 00101, indicating the NTSC
Vsync begin position.
For all NTSC/PAL Vsync timing controls, both the V bit in the
AV code and the Vsync on the VS pin are modified.
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06

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