LSISAS1068 LSI, LSISAS1068 Datasheet - Page 104

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

4-34
31
0
0
0
0
0
0
0
Register: 0x08
Host Diagnostic
Read/Write
The Host Diagnostic register contains diagnostic controls and status
information. This register can only be written when bit 7 of this register
is set. This bit is set by writing the correct key sequence to the
Sequence
PCI Host Register Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
0
0
0
0
register.
0
Reserved
This field is reserved.
Clear Flash Bad Signature
Writing a one (1) to this bit clears the Flash Bad Signature
setting within the LSISAS1068. This bit is self-clearing.
Prevent IOC Boot
Setting this bit prevents the IOP from rebooting after a
reset.
Reserved
This field is reserved.
Diagnostic Write Enable
The LSISAS1068 sets this read only bit when the host
writes the correct Write I/O Key to the
register. The LSISAS1068 clears this bit when the host
writes a value other than the Write I/O Key to the
Sequence
Flash Bad Signature
The LSISAS1068 sets this bit if the IOP ARM966E-S™
processor encounters a bad flash signature when booting
from flash ROM. The LSISAS1068 also sets the DisARM
bit (bit 1 in this register) to hold the IOP ARM processor
in a reset state. The LSISAS1068 maintains this state
until the PCI host clears both the Flash Bad Signature
and DisARM bits.
Reset History
The LSISAS1068 sets this bit if it experiences a Power
On Reset (POR), PCI Reset, or TestReset/.
0
0
Host Diagnostic
0
16 15
0
register.
0
0
0
0
0
0
0
8
0
7
0
0
Write Sequence
1
0
0
Write
0 X 0
[31:11]
Write
10
0
9
8
7
6
5