LSISAS1068 LSI, LSISAS1068 Datasheet - Page 41

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

2.3.2.14
2.3.2.15
2.3.2.16
2.3.2.17
Dual Address Cycles (DAC) Command
Memory Read Line Command
Memory Read Block Command
Memory Write and Invalidate Command
The LSISAS1068 performs Dual Address Cycles (DAC), per the PCI
Local Bus Specification, Version 3.0. The LSISAS1068 supports this
command when operating in either the PCI or PCI-X bus mode.
This command is identical to the Memory Read command except it
additionally indicates that the master intends to fetch a complete cache
line. The LSISAS1068 supports this command when operating in the PCI
mode.
The LSISAS1068 uses this command to read from memory. The
LSISAS1068 supports this command when operating in the PCI-X mode.
The Memory Write and Invalidate command is identical to the Memory
Write command, except it additionally guarantees a minimum transfer of
one complete cache line. The master uses this command when it intends
to write all bytes within the addressed cache line in a single PCI
transaction unless interrupted by the target. This command requires
implementation of the PCI
determines when to issue a Write and Invalidate command instead of a
Memory Write command and supports this command when operating in
the PCI bus mode.
Alignment – The LSISAS1068 uses the calculated line size value to
determine if the current address aligns to the cache line size. If the
address does not align, the LSISAS1068 bursts data using a noncache
command. If the starting address aligns, the LSISAS1068 issues a
Memory Write and Invalidate command using the cache line size as the
burst size.
Multiple Cache Line Transfers – The Memory Write and Invalidate
command can write multiple cache lines of data in a single bus
ownership. The LSISAS1068 issues a burst transfer as soon as it
reaches a cache line boundary. The PCI Local Bus specification states
that the transfer size must be a multiple of the cache line size. The
PCI Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Cache Line Size
register. The LSISAS1068
2-15