LSISAS1068 LSI, LSISAS1068 Datasheet - Page 128

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

Table 5.31
1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations
5-18
Signal
K25
K26
L1
L2
L3
L4
L5
L6
L7
L8
L10
L11
L12
L13
L14
L15
L16
L17
L19
L20
L21
L22
L23
L24
L25
L26
M1
M2
M3
M4
M5
M6
M7
M8
M10
M11
M12
M13
M14
M15
M16
M17
M19
M20
M21
M22
M23
M24
M25
M26
N1
N2
N3
N4
N5
N6
N7
marked RESERVED are for LSI Logic factory test use only. Refer to
Signals”
FAULT_LED[4]/
PBSRAM_CS/
SIO_DOUT_B
SIO_END_B
FLASH_CS/
SIO_CLK_B
SIO_DIN_B
TRST_ICE/
CPCI_LED/
to determine how to terminate the RESERVED pads.
RTCK_ICE
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
TMS_ICE
VDDIO33
TCK_ICE
HB_LED/
MAD[15]
MAD[14]
Listing by Pin Number (Cont.)
BWE[2]/
MWE1/
MOE0/
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
Pin
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N/C
N/C
N/C
N/C
N/C
N/C
Specifications
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Signal
N8
N10
N11
N12
N13
N14
N15
N16
N17
N19
N20
N21
N22
N23
N24
N25
N26
P1
P2
P3
P4
P5
P6
P7
P8
P10
P11
P12
P13
P14
P15
P16
P17
P19
P20
P21
P22
P23
P24
P25
P26
R1
R2
R3
R4
R5
R6
R7
R8
R10
R11
R12
R13
R14
R15
R16
R17
TDIODE_VSS
TDIODE_P
VDDIO33
TDO_ICE
VDDIO33
VDDIO33
VDDIO33
VDDIO33
MADP[1]
MADP[2]
TDI_ICE
BWE[0]/
BWE[1]/
BWE[3]/
GPIO[3]
GPIO[1]
GPIO[0]
GPIO[2]
MWE0/
MCLK
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
TDO
Pin
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N/C
N/C
N/C
N/C
N/C
TDI
1
Signal
R19
R20
R21
R22
R23
R24
R25
R26
T1
T2
T3
T4
T5
T6
T7
T8
T10
T11
T12
T13
T14
T15
T16
T17
T19
T20
T21
T22
T23
T24
T25
T26
U1
U2
U3
U4
U5
U6
U7
U8
U10
U11
U12
U13
U14
U15
U16
U17
U19
U20
U21
U22
U23
U24
U25
U26
V1
CPCI_SWITCH
CPCI_ENUM/
CPCI64_EN/
PROCMON
ALT_INTA/
CPCI_EN/
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
MAD[19]
MAD[29]
MAD[21]
MAD[24]
MAD[17]
MAD[27]
MAD[26]
MAD[16]
MAD[18]
ADSC/
TRST/
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
ADV/
TMS
Pin
VSS
VSS
TCK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N/C
N/C
N/C
N/C
TN/
Section 3.10, “JTAG and Test
Signal
V2
V3
V4
V5
V6
V7
V8
V19
V20
V21
V22
V23
V24
V25
V26
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
RESERVED
RESERVED
BZR_SET
VDDIO33
VDDIO33
VDDIO33
ZCR_EN/
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
MAD[31]
MAD[25]
MAD[23]
MAD[20]
MAD[30]
MAD[22]
MAD[28]
AD[30]
AD[36]
AD[34]
AD[38]
ECC5
ECC3
REQ/
INTA/
IDDT
RST/
Pin
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
N/C
N/C
N/C
N/C
N/C