LSISAS1068 LSI, LSISAS1068 Datasheet - Page 119

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LSISAS1068

Manufacturer Part Number
LSISAS1068
Description
Manufacturer
LSI
Datasheet

Specifications of LSISAS1068

Lead Free Status / RoHS Status
Not Compliant

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5.2
Table 5.23
1.
2.
Symbol Parameter
t
t
t
t
For frequencies above 33 MHz, the clock frequency can not be changed beyond the spread
spectrum limits except while RST/ is asserted.
Duty cycle not to exceed 60/40.
1
2
3
4
AC Characteristics
PCI Bus clock period
PCI CLK LOW time
PCI CLK HIGH time
PCI CLK slew rate
External Clock
The AC characteristics described in this section apply over the entire
range of operating conditions (refer to
Chip timing is based on simulation at worst case voltage, temperature,
and processing. Timing was developed with a load capacitance of 50 pF,
which does not include the PCI/PCI-X pads. The PCI/PCI-X pads are
specified as 10 pF loads.
clock timing data.
Figure 5.1
CLK, SCLK 1.4 V
AC Characteristics
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
2
1
Min
7.5
1.5
133 MHz
3
3
External Clock
PCI-X
Max
20
4
t
t
1
4
t
3
Min
Table 5.23
1.5
15
6
6
66 MHz
PCI-X
t
2
Max
20
4
and
Section 5.1, “DC
Min
1.5
15
6
6
66 MHz
Figure 5.1
PCI
Max
30
4
provide external
Min
30
11
11
Characteristics”).
1
33 MHz
PCI
Max
250
4
Units
V/ns
ns
ns
ns
5-9

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