LSISAS1068 LSI, LSISAS1068 Datasheet - Page 83

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

31
0
0
0
0
0
0
0
Register: 0x30–0x33
Expansion ROM Base Address
Read/Write
This four-byte register contains the base address and size information for
the expansion ROM.
PCI Configuration Space Register Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
0
0
0
0
0
Expansion ROM Base Address
The Subsystem Device ID Control Power-On Sense pin
(MAD[5]) can control the value of bit [15] of this register.
Allowing the Subsystem Device ID Control pin to remain
internally pulled LOW has no effect on this register. Pull-
ing this pin HIGH sets bit [15] of this register. Pulling the
ID Control pin HIGH takes precedence over all other
settings for bit [15].
Refer to
tion,”
Expansion ROM Base Address
These bits correspond to the upper 21 bits of the
expansion ROM base address. The host system detects
the size of the external memory by first writing
0xFFFFFFFF to this register and then reading the
register back. The LSISAS1068 responds with zeros in all
don’t care locations. The least significant one (1) that
remains represents the binary version of the external
memory size. For example, to indicate an external
memory size of 32 Kbytes, this register returns ones in
the upper 17 bits when written with 0xFFFFFFFF and
read back.
Reserved
This field is reserved.
0
0
If the ID Control pin is pulled LOW, this register con-
tains 0x1000.
If the ID Control pin is pulled HIGH, this register con-
tains 0x9000.
for additional information.
0
16 15
Section 3.12, “Power-On Sense Pins Descrip-
0
0
0
0
0
0
0
0
8
0
7
0
0
0
0
0
0
[31:11]
[10:1]
0
4-13
0
0