LSISAS1068 LSI, LSISAS1068 Datasheet - Page 60

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

Table 3.9
3.6
Table 3.10
3-8
Signal Name BGA Position
REFCLK_P,
REFCLK_N
RTRIM
Signal Name BGA Position
MCLK
ADSC/
ADV/
MAD[31:0]
MADP[3:0]
Memory Interface Signals
SAS Interface Signals (Cont.)
Memory Interface Signals
C13,
D12
C14
P23
R21
R23
V23, W24, T21,
W26, U23, U24,
V24, T23, V25,
W25, T22, V26,
R26, U26, T26,
U25, K25, M21,
J25, H25, D26, H24,
K23, G26, E25, J23,
J24, G23, D25, K22,
F26, E26
Y26, P24, N24, J22 I/O
Table 3.10
Signal Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
describes the memory interface signals.
Type Description
I
Type Description
O
O
O
I/O
The Reference Clock signals provide the serial differential
clock. Connect a 75 MHz oscillator with an accuracy of at
least 50ppm to these pins.
To use a single-ended crystal, tie the crystal to REFCLK_P
and tie REFCLK_N to a resistor termination.
This pin provides the analog resistor reference for the
GigaBlaze transceivers.
All synchronous RAM control/data signals reference the
rising edge of the Memory Clock signal. MOE[1:0]/ are
asynchronous inputs and do not reference this clock.
Asserting the active LOW Address-Strobe-Controller
signal initiates read, write, or chip deselect cycles.
Asserting the active LOW Advance signal increments the
burst address counter of the selected synchronous SRAM.
The Multiplexed Address/Data bus signals provide the
address and data bus to the PBSRAM, flash ROM, and
NVSRAM.
These signals also provide Power-On Sense configuration
functions to the LSISAS1068.
Sense Pins Description,”
configuration options.
Provide pull-up resistors for these pins.
The Multiplexed Address/Data Parity signals provide
parity checking for MAD[31:0]. MADP[3] provides parity
protection for the high-order byte (MAD[31:24]). while
MADP[0] provides parity protection for low-order byte
(MADP[7:0]).
describe the Power-On sense
Section 3.12, “Power-On