LSISAS1068 LSI, LSISAS1068 Datasheet - Page 78

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

4-8
Register: 0x0C
Cache Line Size
Read/Write
Register: 0x0D
Latency Timer
Read/Write
PCI Host Register Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
7
0
7
0
X
0
Cache Line Size
This register specifies the system cache line size in units
of 32-bit words. In the conventional PCI mode, the
LSISAS1068 PCI function uses this register to determine
whether to use Write and Invalidate or Write commands
for performing write cycles. Programming this register to
a number other than a nonzero power of two disables the
the use of the PCI performance commands to execute
data transfers. The PCI function ignores this register
when operating in the PCI-X mode.
Reserved
This field is reserved.
Latency Timer
The Latency Timer register specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master. If the LSISAS1068 initializes in the PCI mode, the
default value of this register is 0x00. If the LSISAS1068
initializes in the PCI-X mode, the default value of this reg-
ister is 0x40.
Reserved
This field is reserved.
0
0
Cache Line Size
Latency Timer
0
0
0
0
0
0
0
0
0
0
[7:3]
[2:0]
0
0
[7:4]
[3:0]